feat(ulp): add pulse counter example for lp core

components/hal/esp32c6/include/hal/rtc_io_ll.h

@@ -335,6 +335,12 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
 static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type)
 {
     LP_IO.pin[rtcio_num].int_type = type;
+
+    /* Work around for HW issue,
+       need to also enable this clk, so that LP_IO.status.status_interrupt can get updated,
+       and trigger the interrupt on the LP Core
+    */
+    LP_IO.date.clk_en = 1;
 }
 
 /**

components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h

@@ -89,6 +89,14 @@ void ulp_lp_core_sw_intr_enable(bool enable);
  */
 void ulp_lp_core_sw_intr_clear(void);
 
+/**
+ * @brief Puts the CPU into a wait state until an interrupt is triggered
+ *
+ * @note The CPU will draw less power when in this state compared to actively running
+ *
+ */
+void ulp_lp_core_wait_for_intr(void);
+
 #ifdef __cplusplus
 }
 #endif

components/ulp/lp_core/lp_core/lp_core_utils.c

@@ -145,3 +145,8 @@ void ulp_lp_core_sw_intr_clear(void)
 {
     pmu_ll_lp_clear_sw_intr_status(&PMU);
 }
+
+void ulp_lp_core_wait_for_intr(void)
+{
+    asm volatile("wfi");
+}