From a3ce319a87bba41833cd1bc723b4d82975e98030 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Fri, 19 Jun 2026 11:51:28 +0530 Subject: [PATCH 1/3] fix(esp_rom): correct ESP32-P4 secure boot signature block layout --- .../esp32p4/include/esp32p4/rom/secure_boot.h | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/components/esp_rom/esp32p4/include/esp32p4/rom/secure_boot.h b/components/esp_rom/esp32p4/include/esp32p4/rom/secure_boot.h index 01ebfedc98f..9feba509fca 100644 --- a/components/esp_rom/esp32p4/include/esp32p4/rom/secure_boot.h +++ b/components/esp_rom/esp32p4/include/esp32p4/rom/secure_boot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -88,6 +88,25 @@ struct ets_secure_boot_sig_block { #elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME +#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS +struct __attribute((packed)) ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t sha_version; + uint8_t _reserved2; + uint8_t image_digest[48]; + struct { + struct { + uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 / ETS_ECDSA_CURVE_P384 */ + uint8_t point[96]; /* X followed by Y (both little-endian), plus zero bytes if P192 */ + } key; + uint8_t signature[96]; /* r followed by s (both little-endian) */ + uint8_t padding[951]; + } ecdsa; + uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */ + uint8_t _padding[16]; +}; +#else struct __attribute((packed)) ets_secure_boot_sig_block { uint8_t magic_byte; uint8_t version; @@ -105,6 +124,7 @@ struct __attribute((packed)) ets_secure_boot_sig_block { uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */ uint8_t _padding[16]; }; +#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */ #endif ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); From 783348ad44ad9159b68a631d4854c709a20d17d4 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Thu, 16 Jul 2026 15:05:04 +0530 Subject: [PATCH 2/3] fix(bootloader_support): set SECURE_BOOT_SHA384_EN eFuse on ESP32-P4 Set SECURE_BOOT_SHA384_EN when enabling ECDSA-P384 Secure Boot V2 on ESP32-P4, as done on C5/H4/S31, so that ROM verifies the bootloader using the SHA-384 scheme. The eFuse exists only on the rev >= v3.0 eFuse table, so the Kconfig option is gated on rev >= v3.0. --- components/bootloader/Kconfig.projbuild | 2 ++ .../src/esp32p4/secure_boot_secure_features.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 12decf2f2d8..9e5ed185203 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -590,6 +590,8 @@ menu "Security features" config SECURE_BOOT_ECDSA_KEY_LEN_384_BITS bool "Using ECC curve NISTP384 (Recommended)" depends on SECURE_SIGNED_APPS_ECDSA_V2_SCHEME && SOC_ECDSA_SUPPORT_CURVE_P384 + # ESP32-P4 revisions < v3.0 do not support Secure Boot using ECDSA-P384 + depends on !ESP32P4_SELECTS_REV_LESS_V3 endchoice diff --git a/components/bootloader_support/src/esp32p4/secure_boot_secure_features.c b/components/bootloader_support/src/esp32p4/secure_boot_secure_features.c index d98664dc390..bbb657fba46 100644 --- a/components/bootloader_support/src/esp32p4/secure_boot_secure_features.c +++ b/components/bootloader_support/src/esp32p4/secure_boot_secure_features.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -48,6 +48,10 @@ esp_err_t esp_secure_boot_enable_secure_features(void) esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE); #endif +#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS + esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_SHA384_EN); +#endif + esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN); #ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS From 0a3fe51c69dcef06bef18eb0c6927d44cf2474b4 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Thu, 16 Jul 2026 15:05:49 +0530 Subject: [PATCH 3/3] fix(bootloader_support): enable XTS-AES pseudo rounds for ESP32-P4 Burn XTS_DPA_PSEUDO_LEVEL efuse on P4 (rev >= 3.0) as done for other targets. --- components/bootloader/Kconfig.projbuild | 2 ++ .../src/esp32p4/flash_encryption_secure_features.c | 11 ++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 9e5ed185203..221a05b8c51 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -1154,6 +1154,8 @@ menu "Security features" default y if SECURE_FLASH_ENCRYPTION_MODE_RELEASE default n depends on SECURE_FLASH_ENC_ENABLED && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND + # ESP32-P4 revisions < v3.0 do not support the XTS-AES pseudo rounds function + depends on !ESP32P4_SELECTS_REV_LESS_V3 help If set (default), the bootloader will permanently enable the XTS-AES peripheral's pseudo rounds function. Note: Enabling this config would burn an efuse. diff --git a/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c index e5f8dd18609..30fcf4bf782 100644 --- a/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c +++ b/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,6 +16,7 @@ #include "hal/key_mgr_hal.h" #include "hal/key_mgr_ll.h" #include "hal/mspi_ll.h" +#include "hal/spi_flash_encrypted_ll.h" ESP_LOG_ATTR_TAG(TAG, "flash_encrypt"); @@ -45,6 +46,14 @@ esp_err_t esp_flash_encryption_enable_secure_features(void) esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT); +#if CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC + if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) { + ESP_LOGI(TAG, "Enable XTS-AES pseudo rounds function..."); + uint8_t xts_pseudo_level = CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH; + esp_efuse_write_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count); + } +#endif + #if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS) // This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot // otherwise the Flash Encryption key cannot be read protected