mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-01 18:50:34 +03:00
Merge branch 'fix/some_issue_s31' into 'master'
fix(bt/controller): fixed several controller issues Closes BTQABR2023-689, BTQABR2023-683, BTQABR2023-679, CBI-1964, CBI-1986, CBI-1996, CBI-2015, CBI-2019, CBI-2024, CBI-2025, CBI-2061, and BT-4370 See merge request espressif/esp-idf!48860
This commit is contained in:
Submodule components/bt/controller/lib_esp32s31/esp32s31-bt-lib updated: b0aaf1b1f0...3fe7c1bc6c
@@ -167,6 +167,12 @@ config BT_CTRL_BR_EDR_CPB_RX_EN
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help
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Enable BR/EDR Connectionless Peripheral Broadcast Receive
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config BT_CTRL_BR_EDR_HOLD_EN
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bool "Enable BR/EDR Hold Mode"
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default n
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help
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Enable BR/EDR Hold Mode
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config BT_CTRL_BR_EDR_LK_STORE_EN
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bool "Enable BR/EDR controller link key storage"
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default n
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@@ -197,14 +203,14 @@ menu "TX Power Level settings"
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config BT_CTRL_BR_EDR_TX_PWR_ACL_MIN
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int "Default minimum TX power level for ACL"
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default -13
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range -15 20
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range -24 12
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help
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Minimum BR/EDR transmission power level for ACL.
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config BT_CTRL_BR_EDR_TX_PWR_ACL_MAX
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int "Default maximum TX power level for ACL"
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default 4
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range -15 20
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range -24 12
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help
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Maximum BR/EDR transmission power level for ACL.
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@@ -212,28 +218,28 @@ menu "TX Power Level settings"
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int "Default TX power level for APB"
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depends on BT_CTRL_BR_EDR_APB_EN
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default 4
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range -15 20
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range -24 12
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help
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BR/EDR transmission power level for APB.
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config BT_CTRL_BR_EDR_TX_PWR_PAGE
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int "Default TX power level for Page"
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default 4
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range -15 20
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range -24 12
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help
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BR/EDR transmission power level for Page.
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config BT_CTRL_BR_EDR_TX_PWR_PSCAN
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int "Default TX power level for Page Scan"
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default 4
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range -15 20
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range -24 12
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help
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BR/EDR transmission power level for Page Scan.
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config BT_CTRL_BR_EDR_TX_PWR_ISCAN
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int "Default TX power level for Inquiry Scan"
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default 4
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range -15 20
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range -24 12
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help
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BR/EDR transmission power level for Inquiry Scan.
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@@ -241,7 +247,7 @@ menu "TX Power Level settings"
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int "Default TX power level for CPB"
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depends on BT_CTRL_BR_EDR_CPB_TX_EN
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default 4
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range -15 20
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range -24 12
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help
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BR/EDR transmission power level for CPB.
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@@ -249,7 +255,7 @@ menu "TX Power Level settings"
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int "Default TX power level for Synchronization Train"
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depends on BT_CTRL_BR_EDR_CPB_TX_EN
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default 4
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range -15 20
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range -24 12
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help
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BR/EDR transmission power level for Synchronization Train.
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endmenu
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@@ -59,6 +59,12 @@ extern "C" {
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#define UC_BR_EDR_APB_EXT_PCA_EN 0
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#endif
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#if defined(CONFIG_BT_CTRL_BR_EDR_HOLD_EN) && CONFIG_BT_CTRL_BR_EDR_HOLD_EN
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#define UC_BR_EDR_HOLD_EN 1
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#else
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#define UC_BR_EDR_HOLD_EN 0
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#endif
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#if defined(CONFIG_BT_CTRL_BR_EDR_LK_STORE_EN) && CONFIG_BT_CTRL_BR_EDR_LK_STORE_EN
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#define UC_BR_EDR_LK_STORE_EN 1
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#else
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@@ -110,6 +110,7 @@ extern int bredr_ctrl_feat_sync_en(void);
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extern int bredr_ctrl_feat_apb_en(void);
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extern int bredr_ctrl_feat_bcst_enc_en(void);
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extern int bredr_ctrl_feat_pca_en(void);
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extern int bredr_ctrl_feat_hold_en(void);
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extern int bredr_ctrl_feat_cpb_rx_en(void);
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extern int bredr_ctrl_feat_cpb_tx_en(void);
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extern int bredr_ctrl_feat_dtm_en(void);
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@@ -626,6 +627,14 @@ static int bredr_ctrl_setup_callback(void)
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}
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#endif /* UC_BR_EDR_APB_EXT_PCA_EN */
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#if UC_BR_EDR_HOLD_EN
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ret = bredr_ctrl_feat_hold_en();
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if (ret != 0) {
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ESP_LOGE(BREDR_LOG_TAG, "bredr_ctrl_feat_hold_en failed, ret:%d", ret);
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break;
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}
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#endif /* UC_BR_EDR_HOLD_EN */
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#if UC_BR_EDR_CPB_RX_LINK_NB
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ret = bredr_ctrl_feat_cpb_rx_en();
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if (ret != 0) {
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@@ -17,7 +17,11 @@ wr_btdm_external_bb_get_tx_pwr_table(uint8_t *length, uint8_t modem_cfg)
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assert(length != NULL);
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assert (modem_cfg <= 2);
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// TODO: replace with bt_bb_tx_pwr_table_get when all the targets(h4, s31, etc) support this API
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return bt_bb_get_tx_pwr_table(length);
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if (modem_cfg == 2) { // BREDR
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return bt_bb_tx_pwr_table_get(length, modem_cfg);
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} else {
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return bt_bb_get_tx_pwr_table(length);
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}
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}
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/*
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@@ -113,6 +113,7 @@ hci_h4_sm_w4_header(struct hci_h4_sm *h4sm, struct hci_h4_input_buffer *ib)
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{
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int rc;
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uint16_t conn_handle = 0;
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uint16_t handle_flags = 0;
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rc = hci_h4_ib_pull_min_len(h4sm, ib);
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if (rc) {
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@@ -132,7 +133,19 @@ hci_h4_sm_w4_header(struct hci_h4_sm *h4sm, struct hci_h4_input_buffer *ib)
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h4sm->exp_len = h4sm->hdr[2] + 3;
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break;
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case HCI_H4_ACL:
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conn_handle = btdm_get_le16(&h4sm->hdr[0]) & HCI_INTERNAL_CONN_MASK;
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handle_flags = btdm_get_le16(&h4sm->hdr[0]);
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conn_handle = handle_flags & HCI_INTERNAL_CONN_MASK;
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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if (HCI_INTERNAL_ACL_IS_BREDR_BCAST(handle_flags) || HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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h4sm->exp_len = btdm_get_le16(&h4sm->hdr[2]) + 4;
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h4sm->pkt = h4sm->allocs->bredr_acl(conn_handle);
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if (!h4sm->pkt) {
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return -1;
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}
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memcpy(h4sm->pkt->data, h4sm->hdr, h4sm->len);
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break;
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}
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#endif // UC_BT_CTRL_BR_EDR_IS_ENABLE
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#if UC_BT_CTRL_BLE_IS_ENABLE
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if (HCI_INTERNAL_CONN_IS_BLE(conn_handle)) {
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h4sm->om = h4sm->allocs->acl();
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@@ -147,17 +160,6 @@ hci_h4_sm_w4_header(struct hci_h4_sm *h4sm, struct hci_h4_input_buffer *ib)
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break;
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}
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#endif // UC_BT_CTRL_BLE_IS_ENABLE
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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if (HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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h4sm->exp_len = btdm_get_le16(&h4sm->hdr[2]) + 4;
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h4sm->pkt = h4sm->allocs->bredr_acl(conn_handle);
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if (!h4sm->pkt) {
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return -1;
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}
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memcpy(h4sm->pkt->data, h4sm->hdr, h4sm->len);
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break;
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}
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#endif // UC_BT_CTRL_BR_EDR_IS_ENABLE
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return -1;
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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case HCI_H4_SYNC:
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@@ -226,6 +228,7 @@ hci_h4_sm_w4_payload(struct hci_h4_sm *h4sm,
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struct hci_h4_input_buffer *ib)
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{
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uint16_t len;
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uint16_t handle_flags = 0;
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len = min(ib->len, h4sm->exp_len - h4sm->len);
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switch (h4sm->pkt_type) {
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@@ -246,9 +249,10 @@ hci_h4_sm_w4_payload(struct hci_h4_sm *h4sm,
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}
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break;
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case HCI_H4_ACL:
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uint16_t conn_handle = btdm_get_le16(&h4sm->hdr[0]) & HCI_INTERNAL_CONN_MASK;
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handle_flags = btdm_get_le16(&h4sm->hdr[0]);
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uint16_t conn_handle = handle_flags & HCI_INTERNAL_CONN_MASK;
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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if (HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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if (HCI_INTERNAL_ACL_IS_BREDR_BCAST(handle_flags) || HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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memcpy(&h4sm->pkt->data[h4sm->len], ib->buf, len);
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break;
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}
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@@ -285,11 +289,24 @@ hci_h4_sm_completed(struct hci_h4_sm *h4sm)
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{
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int rc;
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uint8_t data_source = 0xFF;
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uint16_t handle_flags = 0;
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uint16_t conn_handle = 0;
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switch (h4sm->pkt_type) {
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#if CONFIG_BT_CONTROLLER_ENABLED
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case HCI_H4_ACL:
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uint16_t conn_handle = btdm_get_le16(&h4sm->hdr[0]) & HCI_INTERNAL_CONN_MASK;
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handle_flags = btdm_get_le16(&h4sm->hdr[0]);
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conn_handle = handle_flags & HCI_INTERNAL_CONN_MASK;
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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if (HCI_INTERNAL_ACL_IS_BREDR_BCAST(handle_flags) || HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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if (h4sm->buf) {
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rc = h4sm->frame_cb(h4sm->pkt_type, (void *)h4sm->buf, h4sm->len, HCI_DRIVER_BREDR_ACL);
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HCI_TRANS_ASSERT(rc == 0, rc, 0);
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h4sm->buf = NULL;
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}
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break;
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}
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#endif // UC_BT_CTRL_BR_EDR_IS_ENABLE
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#if UC_BT_CTRL_BLE_IS_ENABLE
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if (HCI_INTERNAL_CONN_IS_BLE(conn_handle)) {
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if (h4sm->om) {
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@@ -299,15 +316,6 @@ hci_h4_sm_completed(struct hci_h4_sm *h4sm)
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}
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}
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#endif // UC_BT_CTRL_BLE_IS_ENABLE
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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if (HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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if (h4sm->buf) {
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rc = h4sm->frame_cb(h4sm->pkt_type, (void *)h4sm->buf, h4sm->len, HCI_DRIVER_BREDR_ACL);
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HCI_TRANS_ASSERT(rc == 0, rc, 0);
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h4sm->buf = NULL;
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}
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}
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#endif // UC_BT_CTRL_BR_EDR_IS_ENABLE
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break;
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case HCI_H4_CMD:
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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@@ -364,6 +372,9 @@ hci_h4_sm_completed(struct hci_h4_sm *h4sm)
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static int
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hci_h4_sm_free_buf(struct hci_h4_sm *h4sm)
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{
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uint16_t handle_flags = 0;
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uint16_t conn_handle = 0;
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switch (h4sm->pkt_type) {
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case HCI_H4_CMD:
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if (h4sm->buf) {
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@@ -380,20 +391,21 @@ hci_h4_sm_free_buf(struct hci_h4_sm *h4sm)
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break;
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#endif // (!CONFIG_BT_CONTROLLER_ENABLED)
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case HCI_H4_ACL:
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uint16_t conn_handle = btdm_get_le16(&h4sm->hdr[0]) & HCI_INTERNAL_CONN_MASK;
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if (HCI_INTERNAL_CONN_IS_BLE(conn_handle)) {
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#if UC_BT_CTRL_BLE_IS_ENABLE
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if (h4sm->om) {
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h4sm->frees->acl(h4sm->om);
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h4sm->om = NULL;
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}
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#endif
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} else {
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handle_flags = btdm_get_le16(&h4sm->hdr[0]);
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conn_handle = handle_flags & HCI_INTERNAL_CONN_MASK;
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if (HCI_INTERNAL_ACL_IS_BREDR_BCAST(handle_flags) || HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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if (h4sm->pkt) {
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h4sm->frees->bredr_acl(h4sm->pkt);
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h4sm->pkt = NULL;
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}
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#endif // UC_BT_CTRL_BR_EDR_IS_ENABLE
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} else {
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#if UC_BT_CTRL_BLE_IS_ENABLE
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if (h4sm->om) {
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h4sm->frees->acl(h4sm->om);
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h4sm->om = NULL;
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}
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#endif
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}
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break;
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@@ -180,6 +180,7 @@ hci_driver_vhci_host_tx(hci_driver_data_type_t data_type, uint8_t *data, uint32_
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{
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uint16_t pkt_len;
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uint16_t conn_handle;
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uint16_t handle_flags = 0;
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hci_driver_packet_t *pkt = NULL;
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uint8_t data_source = 0xFF;
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@@ -194,9 +195,12 @@ hci_driver_vhci_host_tx(hci_driver_data_type_t data_type, uint8_t *data, uint32_
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break;
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case HCI_DRIVER_TYPE_ACL:
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conn_handle = btdm_get_le16(&data[1]) & HCI_INTERNAL_CONN_MASK;
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handle_flags = btdm_get_le16(&data[1]);
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conn_handle = handle_flags & HCI_INTERNAL_CONN_MASK;
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bool is_bredr = HCI_INTERNAL_ACL_IS_BREDR_BCAST(handle_flags) ||
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HCI_INTERNAL_CONN_IS_BREDR(conn_handle);
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#if UC_BT_CTRL_BLE_IS_ENABLE
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if (HCI_INTERNAL_CONN_IS_BLE(conn_handle)) {
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if (!is_bredr && HCI_INTERNAL_CONN_IS_BLE(conn_handle)) {
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struct ble_mbuf *om = ble_msys_get_pkthdr(pkt_len, ESP_HCI_INTERNAL_ACL_MBUF_LEADINGSPCAE);
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assert(om);
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assert(ble_mbuf_append(om, &data[1], length - 1) == 0);
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@@ -205,7 +209,7 @@ hci_driver_vhci_host_tx(hci_driver_data_type_t data_type, uint8_t *data, uint32_
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}
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#endif // UC_BT_CTRL_BLE_IS_ENABLE
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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if (HCI_INTERNAL_CONN_IS_BREDR(conn_handle)) {
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if (is_bredr) {
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pkt = btdm_hci_trans_buf_alloc(data_type, conn_handle);
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assert(pkt);
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memcpy(pkt->data, &data[1], pkt_len);
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@@ -130,6 +130,7 @@ typedef int (*btdm_hci_trans_tx_func_t)(hci_driver_packet_t *pkt);
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#define HCI_INTERNAL_CONN_IS_BREDR(conn_handle) (conn_handle & 0x0800)
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#define HCI_INTERNAL_CONN_IS_BREDR_ACL(conn_handle) ((conn_handle & 0x0800) && (conn_handle & 0x000f))
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#define HCI_INTERNAL_CONN_IS_BREDR_SYNC(conn_handle) ((conn_handle & 0x0800) && (conn_handle & 0x00f0))
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#define HCI_INTERNAL_ACL_IS_BREDR_BCAST(handle_flags) (((handle_flags) >> 14 & 0x03) == 0x01)
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int r_btdm_hci_trans_register_tx(btdm_hci_trans_tx_func_t *tx_func, bool async);
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