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Merge branch 'bugfix/fix-driver-8_16bit-reg-access' into 'master'

Browse Source 
bugfix/driver: fix and cleanup soc/ll stuffs

Closes IDF-3722

See merge request espressif/esp-idf!14829
This commit is contained in:
morris
2021-08-30 10:27:05 +00:00
parent f1c6c68f19 892f5e7df3
commit 2e0ffbd543
208 changed files with 1527 additions and 3340 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h2/include/soc/apb_ctrl_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32h2/include/soc/apb_saradc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;
components/soc/esp32h2/include/soc/efuse_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/
union {
struct {
components/soc/esp32h2/include/soc/gdma_struct.h
+1 -1
View File
@@ -19,7 +19,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gdma_dev_s {
struct {
union {
struct {
components/soc/esp32h2/include/soc/gpio_sd_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;
components/soc/esp32h2/include/soc/gpio_struct.h
+1 -1
View File
@@ -18,7 +18,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
union {
struct {
components/soc/esp32h2/include/soc/i2c_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period : 9;
components/soc/esp32h2/include/soc/i2s_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32h2/include/soc/ledc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
components/soc/esp32h2/include/soc/rmt_struct.h
+3 -5
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /**/
union {
struct {
@@ -291,11 +291,9 @@ typedef struct {
} rmt_item32_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[48];
};
rmt_item32_t data32[48];
} chan[4];
} rmt_mem_t;
components/soc/esp32h2/include/soc/rtc_cntl_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
components/soc/esp32h2/include/soc/rtc_i2c_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
components/soc/esp32h2/include/soc/sensitive_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct sensitive_dev_s {
union {
struct {
uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/
components/soc/esp32h2/include/soc/spi_mem_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct spi_mem_dev_s {
union {
struct {
uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/
components/soc/esp32h2/include/soc/spi_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct spi_dev_s {
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
components/soc/esp32h2/include/soc/syscon_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32h2/include/soc/system_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct system_dev_s {
union {
struct {
uint32_t reserved0 : 6; /*reserved*/
components/soc/esp32h2/include/soc/systimer_struct.h
+10
View File
@@ -88,6 +88,7 @@ typedef union {
* update timer_unit0
*/
uint32_t timer_unit_update: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} systimer_unit_op_reg_t;
@@ -102,6 +103,7 @@ typedef struct {
* timer unit load high 32 bit
*/
uint32_t timer_unit_load_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -126,6 +128,7 @@ typedef struct {
* timer target high 32 bit
*/
uint32_t timer_target_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -172,6 +175,7 @@ typedef struct {
* timer read value high 20bit
*/
uint32_t timer_unit_value_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -195,6 +199,7 @@ typedef union {
* timer comp load value
*/
uint32_t timer_comp_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_comp_load_reg_t;
@@ -208,6 +213,7 @@ typedef union {
* timer unit load value
*/
uint32_t timer_unit_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_unit_load_reg_t;
@@ -230,6 +236,7 @@ typedef union {
* interupt2 enable
*/
uint32_t target2_int_ena: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
@@ -251,6 +258,7 @@ typedef union {
* interupt2 raw
*/
uint32_t target2_int_raw: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
@@ -272,6 +280,7 @@ typedef union {
* interupt2 clear
*/
uint32_t target2_int_clr: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;
@@ -293,6 +302,7 @@ typedef union {
* reg_target2_int_st
*/
uint32_t target2_int_st: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_st_reg_t;
components/soc/esp32h2/include/soc/timer_group_reg.h
+23 -23
View File
@@ -35,7 +35,7 @@ extern "C" {
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
@@ -92,7 +92,7 @@ extern "C" {
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
@@ -105,7 +105,7 @@ extern "C" {
/** TIMG_T0HI_REG register
* Timer $x current value, high 22 bits
*/
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
@@ -118,7 +118,7 @@ extern "C" {
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
@@ -130,7 +130,7 @@ extern "C" {
/** TIMG_T0ALARMLO_REG register
* Timer $x alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
@@ -142,7 +142,7 @@ extern "C" {
/** TIMG_T0ALARMHI_REG register
* Timer $x alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
@@ -154,7 +154,7 @@ extern "C" {
/** TIMG_T0LOADLO_REG register
* Timer $x reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
@@ -167,7 +167,7 @@ extern "C" {
/** TIMG_T0LOADHI_REG register
* Timer $x reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
@@ -180,7 +180,7 @@ extern "C" {
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
@@ -193,7 +193,7 @@ extern "C" {
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
@@ -284,7 +284,7 @@ extern "C" {
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
@@ -304,7 +304,7 @@ extern "C" {
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
@@ -316,7 +316,7 @@ extern "C" {
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
@@ -328,7 +328,7 @@ extern "C" {
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
@@ -340,7 +340,7 @@ extern "C" {
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
@@ -352,7 +352,7 @@ extern "C" {
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
@@ -364,7 +364,7 @@ extern "C" {
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
@@ -436,7 +436,7 @@ extern "C" {
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
@@ -455,7 +455,7 @@ extern "C" {
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
@@ -474,7 +474,7 @@ extern "C" {
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
@@ -493,7 +493,7 @@ extern "C" {
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
@@ -539,7 +539,7 @@ extern "C" {
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
@@ -551,7 +551,7 @@ extern "C" {
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
components/soc/esp32h2/include/soc/twai_struct.h
+47 -41
View File
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@@ -61,97 +61,99 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
uint32_t reserved1: 1; /* Internal Reserved */
uint32_t reserved13: 1; /* Internal Reserved */
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@@ -159,45 +161,49 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved24: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
components/soc/esp32h2/include/soc/uart_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte; /*a*/
components/soc/esp32h2/include/soc/uhci_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/
components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct usb_serial_jtag_dev_s {
union {
struct {
uint32_t rdwr_byte : 8; /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */