mirror of
https://github.com/espressif/esp-idf.git
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feat(dma): graduate the dma driver into a single component
This commit is contained in:
morris
@@ -1,783 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "hal/hal_utils.h"
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#include "hal/gdma_types.h"
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#include "hal/gdma_ll.h"
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#include "soc/ahb_dma_struct.h"
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#include "soc/ahb_dma_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
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// any "dummy" peripheral ID can be used for M2M mode
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#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFAC2)
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#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
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///////////////////////////////////// Common /////////////////////////////////////////
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/**
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* @brief Force enable register clock
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*/
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static inline void ahb_dma_ll_force_enable_reg_clock(ahb_dma_dev_t *dev, bool enable)
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{
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dev->misc_conf.clk_en = enable;
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}
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/**
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* @brief Disable priority arbitration
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*
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* @param dev DMA register base address
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* @param dis True to disable, false to enable
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*/
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static inline void ahb_dma_ll_disable_prio_arb(ahb_dma_dev_t *dev, bool dis)
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{
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dev->misc_conf.arb_pri_dis = dis;
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}
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/**
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* @brief Reset DMA FSM
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*
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* @param dev DMA register base address
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*/
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static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev)
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{
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dev->misc_conf.ahbm_rst_inter = 1;
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dev->misc_conf.ahbm_rst_inter = 0;
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}
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/**
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* @brief Preset valid memory range for AHB-DMA
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*
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* @param dev DMA register base address
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*/
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static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev)
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{
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// AHB-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
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dev->intr_mem_start_addr.val = 0x40000000;
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dev->intr_mem_end_addr.val = 0x4FFC0000;
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}
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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/**
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* @brief Enable the weighted arbitration for AHB-DMA
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*
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* @param dev DMA register base address
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* @param enable True to enable, false to disable
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*/
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static inline void ahb_dma_ll_enable_weighted_arb(ahb_dma_dev_t *dev, bool enable)
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{
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dev->weight_en.weight_en = enable;
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}
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/**
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* @brief Set the weighted arbitration timeout for AHB-DMA
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*
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* @param dev DMA register base address
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* @param timeout AHB bus clock cycle
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*/
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static inline void ahb_dma_ll_set_weighted_arb_timeout(ahb_dma_dev_t *dev, uint32_t timeout)
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{
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HAL_ASSERT(timeout != 0 && timeout <= 65535);
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dev->arb_timeout.arb_timeout_num = timeout;
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}
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#endif
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///////////////////////////////////// RX /////////////////////////////////////////
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/**
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* @brief Get DMA RX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw)
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{
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if (raw) {
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return dev->in_intr[channel].raw.val;
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} else {
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return dev->in_intr[channel].st.val;
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}
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}
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/**
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* @brief Enable DMA RX channel interrupt
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*/
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static inline void ahb_dma_ll_rx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->in_intr[channel].ena.val |= mask;
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} else {
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dev->in_intr[channel].ena.val &= ~mask;
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}
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}
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/**
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* @brief Clear DMA RX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->in_intr[channel].clr.val = mask;
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}
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/**
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* @brief Get DMA RX channel interrupt status register address
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*/
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static inline volatile void *ahb_dma_ll_rx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->in_intr[channel].st);
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}
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/**
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* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
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*/
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static inline void ahb_dma_ll_rx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf1.in_check_owner_chn = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading data, disabled by default
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*/
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static inline void ahb_dma_ll_rx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.in_data_burst_en_chn = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
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*/
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static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
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}
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#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
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/**
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* @brief Set RX channel burst size
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*/
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static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz)
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{
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uint8_t burst_mode = 0;
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switch (sz) {
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case 4:
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burst_mode = 0; // single
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break;
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case 16:
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burst_mode = 1; // incr4
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break;
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case 32:
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burst_mode = 2; // incr8
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break;
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case 64:
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burst_mode = 3; // incr16
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break;
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default:
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HAL_ASSERT(false);
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break;
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}
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dev->channel[channel].in.in_conf0.in_data_burst_mode_sel_chn = burst_mode;
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}
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#endif
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/**
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* @brief Reset DMA RX channel FSM and FIFO pointer
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_conf0.in_rst_chn = 1;
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dev->channel[channel].in.in_conf0.in_rst_chn = 0;
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}
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/**
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* @brief Check if DMA RX FIFO is full
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* @param fifo_level only supports level 1
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*/
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static inline bool ahb_dma_ll_rx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x01;
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}
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/**
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* @brief Check if DMA RX FIFO is empty
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* @param fifo_level only supports level 1
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*/
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static inline bool ahb_dma_ll_rx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x02;
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}
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/**
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* @brief Get number of bytes remained in the L1 RX FIFO
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* @param fifo_level only supports level 1
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*/
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static inline uint32_t ahb_dma_ll_rx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.infifo_cnt_chn;
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}
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/**
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* @brief Pop data from DMA RX FIFO
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*/
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static inline uint32_t ahb_dma_ll_rx_pop_data(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_pop.infifo_pop_chn = 1;
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return dev->channel[channel].in.in_pop.infifo_rdata_chn;
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}
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/**
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* @brief Set the descriptor link base address for RX channel
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->in_link_addr[channel].inlink_addr_chn = addr;
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}
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/**
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* @brief Start dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_start(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.inlink_start_chn = 1;
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}
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/**
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* @brief Stop dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_stop(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.inlink_stop_chn = 1;
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}
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/**
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* @brief Restart a new inlink right after the last descriptor
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_rx_restart(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.inlink_restart_chn = 1;
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}
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/**
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* @brief Enable DMA RX to return the address of current descriptor when receives error
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*/
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static inline void ahb_dma_ll_rx_enable_auto_return(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_link.inlink_auto_ret_chn = enable;
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}
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/**
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* @brief Check if DMA RX descriptor FSM is in IDLE state
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*/
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static inline bool ahb_dma_ll_rx_is_desc_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_link.inlink_park_chn;
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}
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/**
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* @brief Get RX success EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_success_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_suc_eof_des_addr.val;
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}
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/**
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* @brief Get RX error EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_error_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_err_eof_des_addr.val;
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}
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/**
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* @brief Get the pre-fetched RX descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_rx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_dscr.val;
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}
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/**
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* @brief Set priority for DMA RX channel
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*/
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static inline void ahb_dma_ll_rx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio)
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{
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dev->channel[channel].in.in_pri.rx_pri_chn = prio;
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}
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/**
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* @brief Connect DMA RX channel to a given peripheral
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*/
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static inline void ahb_dma_ll_rx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
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{
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dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
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dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
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}
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/**
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* @brief Disconnect DMA RX channel from peripheral
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*/
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static inline void ahb_dma_ll_rx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
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dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
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}
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/**
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* @brief Whether to enable the ETM subsystem for RX channel
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*
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* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
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*/
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static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.in_etm_en_chn = enable;
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}
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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/**
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* @brief Enable the weighted arbitration optimize for DMA RX channel
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*
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* @param dev DMA register base address
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* @param channel Channel ID
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* @param enable True to enable, false to disable
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*/
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static inline void ahb_dma_ll_rx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->in_crc_arb[channel].arb_weight_opt.rx_arb_weight_opt_dis_chn = !enable;
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}
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/**
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* @brief Set the weight for DMA RX channel
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*
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* @param dev DMA register base address
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* @param channel Channel ID
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* @param weight Weight value
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*/
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static inline void ahb_dma_ll_rx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight)
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{
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dev->in_crc_arb[channel].ch_arb_weight.rx_arb_weight_value_chn = weight;
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}
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#endif
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///////////////////////////////////// TX /////////////////////////////////////////
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/**
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* @brief Get DMA TX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t ahb_dma_ll_tx_get_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, bool raw)
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{
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if (raw) {
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return dev->out_intr[channel].raw.val;
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} else {
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return dev->out_intr[channel].st.val;
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}
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}
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/**
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* @brief Enable DMA TX channel interrupt
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*/
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static inline void ahb_dma_ll_tx_enable_interrupt(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->out_intr[channel].ena.val |= mask;
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} else {
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dev->out_intr[channel].ena.val &= ~mask;
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}
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}
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/**
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* @brief Clear DMA TX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void ahb_dma_ll_tx_clear_interrupt_status(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->out_intr[channel].clr.val = mask;
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}
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/**
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* @brief Get DMA TX channel interrupt status register address
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*/
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static inline volatile void *ahb_dma_ll_tx_get_interrupt_status_reg(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->out_intr[channel].st);
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}
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/**
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* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
|
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*/
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static inline void ahb_dma_ll_tx_enable_owner_check(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf1.out_check_owner_chn = enable;
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}
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/**
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* @brief Enable DMA TX channel burst sending data, disabled by default
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*/
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static inline void ahb_dma_ll_tx_enable_data_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.out_data_burst_en_chn = enable;
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}
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/**
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* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
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*/
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static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable;
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}
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#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
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/**
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* @brief Set TX channel burst size
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||||
*/
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static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz)
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||||
{
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uint8_t burst_mode = 0;
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switch (sz) {
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case 4:
|
||||
burst_mode = 0; // single
|
||||
break;
|
||||
case 16:
|
||||
burst_mode = 1; // incr4
|
||||
break;
|
||||
case 32:
|
||||
burst_mode = 2; // incr8
|
||||
break;
|
||||
case 64:
|
||||
burst_mode = 3; // incr16
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
dev->channel[channel].out.out_conf0.out_data_burst_mode_sel_chn = burst_mode;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set TX channel EOF mode
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_set_eof_mode(ahb_dma_dev_t *dev, uint32_t channel, uint32_t mode)
|
||||
{
|
||||
dev->channel[channel].out.out_conf0.out_eof_mode_chn = mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_enable_auto_write_back(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->channel[channel].out.out_conf0.out_auto_wrback_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset DMA TX channel FSM and FIFO pointer
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ahb_dma_ll_tx_reset_channel(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->channel[channel].out.out_conf0.out_rst_chn = 1;
|
||||
dev->channel[channel].out.out_conf0.out_rst_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX FIFO is full
|
||||
* @param fifo_level only supports level 1
|
||||
*/
|
||||
static inline bool ahb_dma_ll_tx_is_fifo_full(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
|
||||
{
|
||||
return dev->channel[channel].out.outfifo_status.val & 0x01;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX FIFO is empty
|
||||
* @param fifo_level only supports level 1
|
||||
*/
|
||||
static inline bool ahb_dma_ll_tx_is_fifo_empty(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
|
||||
{
|
||||
return dev->channel[channel].out.outfifo_status.val & 0x02;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get number of bytes in TX FIFO
|
||||
* @param fifo_level only supports level 1
|
||||
*/
|
||||
static inline uint32_t ahb_dma_ll_tx_get_fifo_bytes(ahb_dma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
|
||||
{
|
||||
return dev->channel[channel].out.outfifo_status.outfifo_cnt_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Push data into DMA TX FIFO
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_push_data(ahb_dma_dev_t *dev, uint32_t channel, uint32_t data)
|
||||
{
|
||||
dev->channel[channel].out.out_push.outfifo_wdata_chn = data;
|
||||
dev->channel[channel].out.out_push.outfifo_push_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the descriptor link base address for TX channel
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ahb_dma_ll_tx_set_desc_addr(ahb_dma_dev_t *dev, uint32_t channel, uint32_t addr)
|
||||
{
|
||||
dev->out_link_addr[channel].outlink_addr_chn = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start dealing with TX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ahb_dma_ll_tx_start(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->channel[channel].out.out_link.outlink_start_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop dealing with TX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ahb_dma_ll_tx_stop(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->channel[channel].out.out_link.outlink_stop_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restart a new outlink right after the last descriptor
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void ahb_dma_ll_tx_restart(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->channel[channel].out.out_link.outlink_restart_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX descriptor FSM is in IDLE state
|
||||
*/
|
||||
static inline bool ahb_dma_ll_tx_is_desc_fsm_idle(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->channel[channel].out.out_link.outlink_park_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TX EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t ahb_dma_ll_tx_get_eof_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->channel[channel].out.out_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the pre-fetched TX descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t ahb_dma_ll_tx_get_prefetched_desc_addr(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->channel[channel].out.out_dscr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set priority for DMA TX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_set_priority(ahb_dma_dev_t *dev, uint32_t channel, uint32_t prio)
|
||||
{
|
||||
dev->channel[channel].out.out_pri.tx_pri_chn = prio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect DMA TX channel to a given peripheral
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_connect_to_periph(ahb_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
|
||||
{
|
||||
(void)periph;
|
||||
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disconnect DMA TX channel from peripheral
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_disconnect_from_periph(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the ETM subsystem for TX channel
|
||||
*
|
||||
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->channel[channel].out.out_conf0.out_etm_en_chn = enable;
|
||||
}
|
||||
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
/**
|
||||
* @brief Enable the weighted arbitration optimize for DMA TX channel
|
||||
*
|
||||
* @param dev DMA register base address
|
||||
* @param channel Channel ID
|
||||
* @param enable True to enable, false to disable
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out_crc_arb[channel].arb_weight_opt.tx_arb_weight_opt_dis_chn = !enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the weight for DMA TX channel
|
||||
*
|
||||
* @param dev DMA register base address
|
||||
* @param channel Channel ID
|
||||
* @param weight Weight value
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight)
|
||||
{
|
||||
dev->out_crc_arb[channel].ch_arb_weight.tx_arb_weight_value_chn = weight;
|
||||
}
|
||||
#endif
|
||||
|
||||
///////////////////////////////////// CRC-TX /////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Clear the CRC result for the TX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out_crc_arb[channel].crc_clear.out_crc_clear_chn_reg = 1;
|
||||
dev->out_crc_arb[channel].crc_clear.out_crc_clear_chn_reg = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC width for TX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_crc_set_width(ahb_dma_dev_t *dev, uint32_t channel, uint32_t width)
|
||||
{
|
||||
HAL_ASSERT(width <= 32);
|
||||
dev->out_crc_arb[channel].crc_width.tx_crc_width_chn = (width - 1) / 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC initial value for TX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t channel, uint32_t value)
|
||||
{
|
||||
dev->out_crc_arb[channel].crc_init_data.out_crc_init_data_chn = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result for TX channel
|
||||
*/
|
||||
static inline uint32_t ahb_dma_ll_tx_crc_get_result(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out_crc_arb[channel].crc_final_result.out_crc_final_result_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Latch the CRC configuration to the hardware, TX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out_crc_arb[channel].crc_width.tx_crc_latch_flag_chn = 1;
|
||||
dev->out_crc_arb[channel].crc_width.tx_crc_latch_flag_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_tx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
|
||||
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
|
||||
{
|
||||
dev->out_crc_arb[channel].crc_en_addr.tx_crc_en_addr_chn = crc_bit;
|
||||
dev->out_crc_arb[channel].crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
|
||||
dev->out_crc_arb[channel].crc_data_en_addr.tx_crc_data_en_addr_chn = crc_bit;
|
||||
if (reverse_data_mask) {
|
||||
// "& 0xff" because the hardware only support 8-bit data
|
||||
data_mask = hal_utils_bitwise_reverse8(data_mask & 0xFF);
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->out_crc_arb[channel].crc_data_en_wr_data, tx_crc_data_en_wr_data_chn, data_mask);
|
||||
}
|
||||
|
||||
///////////////////////////////////// CRC-RX /////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Clear the CRC result for the RX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_rx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in_crc_arb[channel].crc_clear.in_crc_clear_chn_reg = 1;
|
||||
dev->in_crc_arb[channel].crc_clear.in_crc_clear_chn_reg = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC width for RX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_rx_crc_set_width(ahb_dma_dev_t *dev, uint32_t channel, uint32_t width)
|
||||
{
|
||||
HAL_ASSERT(width <= 32);
|
||||
dev->in_crc_arb[channel].crc_width.rx_crc_width_chn = (width - 1) / 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC initial value for RX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_rx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t channel, uint32_t value)
|
||||
{
|
||||
dev->in_crc_arb[channel].crc_init_data.in_crc_init_data_chn = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result for RX channel
|
||||
*/
|
||||
static inline uint32_t ahb_dma_ll_rx_crc_get_result(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in_crc_arb[channel].crc_final_result.in_crc_final_result_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Latch the CRC configuration to the hardware, RX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_rx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in_crc_arb[channel].crc_width.rx_crc_latch_flag_chn = 1;
|
||||
dev->in_crc_arb[channel].crc_width.rx_crc_latch_flag_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_rx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
|
||||
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
|
||||
{
|
||||
dev->in_crc_arb[channel].crc_en_addr.rx_crc_en_addr_chn = crc_bit;
|
||||
dev->in_crc_arb[channel].crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;
|
||||
dev->in_crc_arb[channel].crc_data_en_addr.rx_crc_data_en_addr_chn = crc_bit;
|
||||
if (reverse_data_mask) {
|
||||
// "& 0xff" because the hardware only support 8-bit data
|
||||
data_mask = hal_utils_bitwise_reverse8(data_mask & 0xFF);
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->in_crc_arb[channel].crc_data_en_wr_data, rx_crc_data_en_wr_data_chn, data_mask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,670 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/hal_utils.h"
|
||||
#include "hal/gdma_types.h"
|
||||
#include "hal/gdma_ll.h"
|
||||
#include "soc/axi_dma_struct.h"
|
||||
#include "soc/axi_dma_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AXI_DMA_LL_GET_HW(id) (((id) == 0) ? (&AXI_DMA) : NULL)
|
||||
|
||||
// any "dummy" peripheral ID can be used for M2M mode
|
||||
#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
|
||||
#define AXI_DMA_LL_INVALID_PERIPH_ID (0x3F)
|
||||
|
||||
///////////////////////////////////// Common /////////////////////////////////////////
|
||||
/**
|
||||
* @brief Force enable register clock
|
||||
*/
|
||||
static inline void axi_dma_ll_force_enable_reg_clock(axi_dma_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->misc_conf.clk_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable priority arbitration
|
||||
*
|
||||
* @param dev DMA register base address
|
||||
* @param dis True to disable, false to enable
|
||||
*/
|
||||
static inline void axi_dma_ll_disable_prio_arb(axi_dma_dev_t *dev, bool dis)
|
||||
{
|
||||
dev->misc_conf.arb_pri_dis = dis;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset DMA FSM (Read and Write)
|
||||
*
|
||||
* @param dev DMA register base address
|
||||
*/
|
||||
static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev)
|
||||
{
|
||||
dev->misc_conf.axim_rst_rd_inter = 1;
|
||||
dev->misc_conf.axim_rst_rd_inter = 0;
|
||||
dev->misc_conf.axim_rst_wr_inter = 1;
|
||||
dev->misc_conf.axim_rst_wr_inter = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preset valid memory range for AXI-DMA
|
||||
*
|
||||
* @param dev DMA register base address
|
||||
*/
|
||||
static inline void axi_dma_ll_set_default_memory_range(axi_dma_dev_t *dev)
|
||||
{
|
||||
// AXI-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
|
||||
dev->intr_mem_start_addr.val = 0x4FC00000;
|
||||
dev->intr_mem_end_addr.val = 0x4FFC0000;
|
||||
dev->extr_mem_start_addr.val = 0x40000000;
|
||||
dev->extr_mem_end_addr.val = 0x4C000000;
|
||||
}
|
||||
|
||||
///////////////////////////////////// RX /////////////////////////////////////////
|
||||
/**
|
||||
* @brief Get DMA RX channel interrupt status word
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, bool raw)
|
||||
{
|
||||
if (raw) {
|
||||
return dev->in[channel].intr.raw.val;
|
||||
} else {
|
||||
return dev->in[channel].intr.st.val;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel interrupt
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_interrupt(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->in[channel].intr.ena.val |= mask;
|
||||
} else {
|
||||
dev->in[channel].intr.ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DMA RX channel interrupt
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_clear_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask)
|
||||
{
|
||||
dev->in[channel].intr.clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DMA RX channel interrupt status register address
|
||||
*/
|
||||
static inline volatile void *axi_dma_ll_rx_get_interrupt_status_reg(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return (volatile void *)(&dev->in[channel].intr.st);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_conf1.in_check_owner_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel burst reading data, always enabled
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_descriptor_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.indscr_burst_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the RX channel burst size
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_set_burst_size(axi_dma_dev_t *dev, uint32_t channel, uint32_t sz)
|
||||
{
|
||||
HAL_ASSERT(sz >= 8 && sz <= 128);
|
||||
int ctz = __builtin_ctz(sz);
|
||||
dev->in[channel].conf.in_conf0.in_burst_size_sel_chn = ctz - 3;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset DMA RX channel FSM and FIFO pointer
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_reset_channel(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.in_rst_chn = 1;
|
||||
dev->in[channel].conf.in_conf0.in_rst_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Pop data from DMA RX FIFO
|
||||
*/
|
||||
static inline uint32_t axi_dma_ll_rx_pop_data(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_pop.infifo_pop_chn = 1;
|
||||
return dev->in[channel].conf.in_pop.infifo_rdata_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the descriptor link base address for RX channel
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_set_desc_addr(axi_dma_dev_t *dev, uint32_t channel, uint32_t addr)
|
||||
{
|
||||
dev->in[channel].conf.in_link2.inlink_addr_chn = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start dealing with RX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_start(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_start_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop dealing with RX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_stop(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_stop_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the RX channel, stop the undergoing transfer immediately
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_abort(axi_dma_dev_t *dev, uint32_t channel, bool abort)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.in_cmd_disable_chn = abort;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restart a new inlink right after the last descriptor
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_rx_restart(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_restart_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA RX to return the address of current descriptor when receives error
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_auto_return(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_link1.inlink_auto_ret_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA RX descriptor FSM is in IDLE state
|
||||
*/
|
||||
static inline bool axi_dma_ll_rx_is_desc_fsm_idle(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_link1.inlink_park_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RX success EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_success_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_suc_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RX error EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_error_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_err_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the pre-fetched RX descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_rx_get_prefetched_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].conf.in_dscr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set priority for DMA RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_set_priority(axi_dma_dev_t *dev, uint32_t channel, uint32_t prio)
|
||||
{
|
||||
dev->in[channel].conf.in_pri.rx_pri_chn = prio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect DMA RX channel to a given peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
|
||||
{
|
||||
dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = periph_id;
|
||||
dev->in[channel].conf.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disconnect DMA RX channel from peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].conf.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
|
||||
dev->in[channel].conf.in_conf0.mem_trans_en_chn = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the ETM subsystem for RX channel
|
||||
*
|
||||
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.in_etm_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable access to ecc or aes memory
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->in[channel].conf.in_conf0.in_ecc_aes_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if the channel is ready to be reset
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool axi_dma_ll_rx_is_reset_avail(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in_reset_avail_chn[channel].in_reset_avail_chn;
|
||||
}
|
||||
|
||||
///////////////////////////////////// TX /////////////////////////////////////////
|
||||
/**
|
||||
* @brief Get DMA TX channel interrupt status word
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_tx_get_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, bool raw)
|
||||
{
|
||||
if (raw) {
|
||||
return dev->out[channel].intr.raw.val;
|
||||
} else {
|
||||
return dev->out[channel].intr.st.val;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel interrupt
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_interrupt(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
|
||||
{
|
||||
if (enable) {
|
||||
dev->out[channel].intr.ena.val |= mask;
|
||||
} else {
|
||||
dev->out[channel].intr.ena.val &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear DMA TX channel interrupt
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_clear_interrupt_status(axi_dma_dev_t *dev, uint32_t channel, uint32_t mask)
|
||||
{
|
||||
dev->out[channel].intr.clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DMA TX channel interrupt status register address
|
||||
*/
|
||||
static inline volatile void *axi_dma_ll_tx_get_interrupt_status_reg(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return (volatile void *)(&dev->out[channel].intr.st);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_owner_check(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf1.out_check_owner_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel burst sending data, always enabled
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_data_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_descriptor_burst(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.outdscr_burst_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the TX channel burst size
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_set_burst_size(axi_dma_dev_t *dev, uint32_t channel, uint32_t sz)
|
||||
{
|
||||
HAL_ASSERT(sz >= 8 && sz <= 128);
|
||||
int ctz = __builtin_ctz(sz);
|
||||
dev->out[channel].conf.out_conf0.out_burst_size_sel_chn = ctz - 3;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set TX channel EOF mode
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_set_eof_mode(axi_dma_dev_t *dev, uint32_t channel, uint32_t mode)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_eof_mode_chn = mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_auto_write_back(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_auto_wrback_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset DMA TX channel FSM and FIFO pointer
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_reset_channel(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_rst_chn = 1;
|
||||
dev->out[channel].conf.out_conf0.out_rst_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Push data into DMA TX FIFO
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_push_data(axi_dma_dev_t *dev, uint32_t channel, uint32_t data)
|
||||
{
|
||||
dev->out[channel].conf.out_push.outfifo_wdata_chn = data;
|
||||
dev->out[channel].conf.out_push.outfifo_push_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the descriptor link base address for TX channel
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_set_desc_addr(axi_dma_dev_t *dev, uint32_t channel, uint32_t addr)
|
||||
{
|
||||
dev->out[channel].conf.out_link2.outlink_addr_chn = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start dealing with TX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_start(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_link1.outlink_start_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop dealing with TX descriptors
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_stop(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_link1.outlink_stop_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the TX channel, stop the undergoing transfer immediately
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_abort(axi_dma_dev_t *dev, uint32_t channel, bool abort)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_cmd_disable_chn = abort;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restart a new outlink right after the last descriptor
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void axi_dma_ll_tx_restart(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_link1.outlink_restart_chn = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX descriptor FSM is in IDLE state
|
||||
*/
|
||||
static inline bool axi_dma_ll_tx_is_desc_fsm_idle(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].conf.out_link1.outlink_park_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TX EOF descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_tx_get_eof_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].conf.out_eof_des_addr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the pre-fetched TX descriptor's address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t axi_dma_ll_tx_get_prefetched_desc_addr(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].conf.out_dscr.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set priority for DMA TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_set_priority(axi_dma_dev_t *dev, uint32_t channel, uint32_t prio)
|
||||
{
|
||||
dev->out[channel].conf.out_pri.tx_pri_chn = prio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect DMA TX channel to a given peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_connect_to_periph(axi_dma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
|
||||
{
|
||||
(void)periph;
|
||||
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = periph_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disconnect DMA TX channel from peripheral
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_disconnect_from_periph(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].conf.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable the ETM subsystem for TX channel
|
||||
*
|
||||
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_etm_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Whether to enable access to ecc or aes memory
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
|
||||
{
|
||||
dev->out[channel].conf.out_conf0.out_ecc_aes_en_chn = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if the channel is ready to be reset
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool axi_dma_ll_tx_is_reset_avail(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out_reset_avail_chn[channel].out_reset_avail_chn;
|
||||
}
|
||||
|
||||
///////////////////////////////////// CRC-TX /////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Clear the CRC result for the TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_clear(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].crc.out_crc_clear.out_crc_clear_chn_reg = 1;
|
||||
dev->out[channel].crc.out_crc_clear.out_crc_clear_chn_reg = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC width for TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_set_width(axi_dma_dev_t *dev, uint32_t channel, uint32_t width)
|
||||
{
|
||||
HAL_ASSERT(width <= 16);
|
||||
dev->out[channel].crc.tx_crc_width.tx_crc_width_chn = (width - 1) / 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC initial value for TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_set_init_value(axi_dma_dev_t *dev, uint32_t channel, uint32_t value)
|
||||
{
|
||||
dev->out[channel].crc.out_crc_init_data.out_crc_init_data_chn = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result for TX channel
|
||||
*/
|
||||
static inline uint32_t axi_dma_ll_tx_crc_get_result(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].crc.out_crc_final_result.out_crc_final_result_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Latch the CRC configuration to the hardware, TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_latch_config(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].crc.tx_crc_width.tx_crc_latch_flag_chn = 1;
|
||||
dev->out[channel].crc.tx_crc_width.tx_crc_latch_flag_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
|
||||
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
|
||||
{
|
||||
dev->out[channel].crc.tx_crc_en_addr.tx_crc_en_addr_chn = crc_bit;
|
||||
dev->out[channel].crc.tx_crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
|
||||
dev->out[channel].crc.tx_crc_data_en_addr.tx_crc_data_en_addr_chn = crc_bit;
|
||||
if (reverse_data_mask) {
|
||||
// "& 0xff" because the hardware only support 8-bit data
|
||||
data_mask = hal_utils_bitwise_reverse8(data_mask & 0xFF);
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->out[channel].crc.tx_crc_data_en_wr_data, tx_crc_data_en_wr_data_chn, data_mask);
|
||||
}
|
||||
|
||||
///////////////////////////////////// CRC-RX /////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Clear the CRC result for the RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_clear(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].crc.in_crc_clear.in_crc_clear_chn_reg = 1;
|
||||
dev->in[channel].crc.in_crc_clear.in_crc_clear_chn_reg = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC width for RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_set_width(axi_dma_dev_t *dev, uint32_t channel, uint32_t width)
|
||||
{
|
||||
HAL_ASSERT(width <= 16);
|
||||
dev->in[channel].crc.rx_crc_width.rx_crc_width_chn = (width - 1) / 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC initial value for RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_set_init_value(axi_dma_dev_t *dev, uint32_t channel, uint32_t value)
|
||||
{
|
||||
dev->in[channel].crc.in_crc_init_data.in_crc_init_data_chn = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result for RX channel
|
||||
*/
|
||||
static inline uint32_t axi_dma_ll_rx_crc_get_result(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].crc.in_crc_final_result.in_crc_final_result_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Latch the CRC configuration to the hardware, RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_latch_config(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].crc.rx_crc_width.rx_crc_latch_flag_chn = 1;
|
||||
dev->in[channel].crc.rx_crc_width.rx_crc_latch_flag_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
|
||||
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
|
||||
{
|
||||
dev->in[channel].crc.rx_crc_en_addr.rx_crc_en_addr_chn = crc_bit;
|
||||
dev->in[channel].crc.rx_crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;
|
||||
dev->in[channel].crc.rx_crc_data_en_addr.rx_crc_data_en_addr_chn = crc_bit;
|
||||
if (reverse_data_mask) {
|
||||
// "& 0xff" because the hardware only support 8-bit data
|
||||
data_mask = hal_utils_bitwise_reverse8(data_mask & 0xFF);
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->in[channel].crc.rx_crc_data_en_wr_data, rx_crc_data_en_wr_data_chn, data_mask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,156 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief The contents defined in this file are common for both AXI-DMA and AHB-DMA
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/hp_sys_clkrst_struct.h"
|
||||
#include "soc/soc_etm_source.h"
|
||||
#include "hal/config.h"
|
||||
|
||||
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
|
||||
|
||||
#define GDMA_LL_RX_EVENT_MASK (0x1F)
|
||||
#define GDMA_LL_TX_EVENT_MASK (0x0F)
|
||||
|
||||
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
|
||||
|
||||
#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3)
|
||||
#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
|
||||
#define GDMA_LL_EVENT_TX_EOF (1<<1)
|
||||
#define GDMA_LL_EVENT_TX_DONE (1<<0)
|
||||
|
||||
#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
|
||||
#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
|
||||
#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
|
||||
#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
|
||||
#define GDMA_LL_EVENT_RX_DONE (1<<0)
|
||||
|
||||
#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0
|
||||
#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups
|
||||
#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group
|
||||
|
||||
#define GDMA_LL_AXI_GROUP_START_ID 1 // AXI GDMA group ID starts from 1
|
||||
#define GDMA_LL_AXI_NUM_GROUPS 1 // Number of AXI GDMA groups
|
||||
#define GDMA_LL_AXI_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AXI group
|
||||
|
||||
#define GDMA_LL_PARALLEL_CRC_DATA_WIDTH 8 // Parallel CRC data width is fixed to 8bits
|
||||
#define GDMA_LL_AHB_MAX_CRC_BIT_WIDTH 32 // Max CRC bit width supported by AHB GDMA
|
||||
#define GDMA_LL_AXI_MAX_CRC_BIT_WIDTH 16 // Max CRC bit width supported by AXI GDMA
|
||||
|
||||
#define GDMA_LL_AHB_DESC_ALIGNMENT 4
|
||||
#define GDMA_LL_AXI_DESC_ALIGNMENT 8
|
||||
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 128 // PSRAM controller doesn't support burst access with size > 128 bytes
|
||||
|
||||
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
|
||||
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
|
||||
#endif
|
||||
|
||||
#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \
|
||||
(uint32_t[2][GDMA_ETM_EVENT_MAX]){ \
|
||||
{ \
|
||||
[GDMA_ETM_EVENT_EOF] = PDMA_AHB_EVT_OUT_EOF_CH0 + (chan), \
|
||||
}, \
|
||||
{ \
|
||||
[GDMA_ETM_EVENT_EOF] = PDMA_AXI_EVT_OUT_EOF_CH0 + (chan), \
|
||||
}, \
|
||||
}[group][event]
|
||||
|
||||
#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \
|
||||
(uint32_t[2][GDMA_ETM_EVENT_MAX]){ \
|
||||
{ \
|
||||
[GDMA_ETM_EVENT_EOF] = PDMA_AHB_EVT_IN_SUC_EOF_CH0 + (chan), \
|
||||
}, \
|
||||
{ \
|
||||
[GDMA_ETM_EVENT_EOF] = PDMA_AXI_EVT_IN_SUC_EOF_CH0 + (chan), \
|
||||
}, \
|
||||
}[group][event]
|
||||
|
||||
#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \
|
||||
(uint32_t[2][GDMA_ETM_TASK_MAX]){ \
|
||||
{ \
|
||||
[GDMA_ETM_TASK_START] = PDMA_AHB_TASK_OUT_START_CH0 + (chan), \
|
||||
}, \
|
||||
{ \
|
||||
[GDMA_ETM_TASK_START] = PDMA_AXI_TASK_OUT_START_CH0 + (chan), \
|
||||
}, \
|
||||
}[group][task]
|
||||
|
||||
#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \
|
||||
(uint32_t[2][GDMA_ETM_TASK_MAX]){ \
|
||||
{ \
|
||||
[GDMA_ETM_TASK_START] = PDMA_AHB_TASK_IN_START_CH0 + (chan), \
|
||||
}, \
|
||||
{ \
|
||||
[GDMA_ETM_TASK_START] = PDMA_AXI_TASK_IN_START_CH0 + (chan), \
|
||||
}, \
|
||||
}[group][task]
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the bus clock for the DMA module
|
||||
*/
|
||||
static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable)
|
||||
{
|
||||
if (group_id == 0) {
|
||||
HP_SYS_CLKRST.soc_clk_ctrl1.reg_ahb_pdma_sys_clk_en = enable;
|
||||
} else {
|
||||
HP_SYS_CLKRST.soc_clk_ctrl1.reg_axi_pdma_sys_clk_en = enable;
|
||||
}
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define gdma_ll_enable_bus_clock(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_gdma_ll_enable_bus_clock(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Check if the bus clock is enabled for the DMA module
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool gdma_ll_is_bus_clock_enabled(int group_id)
|
||||
{
|
||||
if (group_id == 0) {
|
||||
return HP_SYS_CLKRST.soc_clk_ctrl1.reg_ahb_pdma_sys_clk_en;
|
||||
} else {
|
||||
return HP_SYS_CLKRST.soc_clk_ctrl1.reg_axi_pdma_sys_clk_en;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the DMA module
|
||||
*/
|
||||
static inline void _gdma_ll_reset_register(int group_id)
|
||||
{
|
||||
if (group_id == 0) {
|
||||
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_ahb_pdma = 1;
|
||||
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_ahb_pdma = 0;
|
||||
} else {
|
||||
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_axi_pdma = 1;
|
||||
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_axi_pdma = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
|
||||
#define gdma_ll_reset_register(...) do { \
|
||||
(void)__DECLARE_RCC_ATOMIC_ENV; \
|
||||
_gdma_ll_reset_register(__VA_ARGS__); \
|
||||
} while(0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user