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ci(parlio_rx): fixed the parlio rx spi test case

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This commit is contained in:
Chen Jichang
2026-07-30 11:35:35 +08:00
parent 6c0c836148
commit 2dd14289c3
18 changed files with 110 additions and 199 deletions
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components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h
+2
View File
@@ -74,6 +74,7 @@ static inline void parlio_ll_enable_bus_clock(int group_id, bool enable)
*
* @param group_id The group id of the parlio module
*/
__attribute__((always_inline))
static inline void parlio_ll_reset_register(int group_id)
{
(void)group_id;
@@ -89,6 +90,7 @@ static inline void parlio_ll_reset_register(int group_id)
* @param dev Parallel IO register base address
* @param src Clock source
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
{
(void)dev;
components/esp_hal_parlio/esp32c6/include/hal/parlio_ll.h
+2
View File
@@ -72,6 +72,7 @@ static inline void parlio_ll_enable_bus_clock(int group_id, bool enable)
*
* @param group_id The group id of the parlio module
*/
__attribute__((always_inline))
static inline void parlio_ll_reset_register(int group_id)
{
(void)group_id;
@@ -87,6 +88,7 @@ static inline void parlio_ll_reset_register(int group_id)
* @param dev Parallel IO register base address
* @param src Clock source
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
{
(void)dev;
components/esp_hal_parlio/esp32h2/include/hal/parlio_ll.h
+2
View File
@@ -76,6 +76,7 @@ static inline void parlio_ll_enable_bus_clock(int group_id, bool enable)
*
* @param group_id The group id of the parlio module
*/
__attribute__((always_inline))
static inline void parlio_ll_reset_register(int group_id)
{
(void)group_id;
@@ -91,6 +92,7 @@ static inline void parlio_ll_reset_register(int group_id)
* @param dev Parallel IO register base address
* @param src Clock source
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
{
(void)dev;
components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h
+2
View File
@@ -74,6 +74,7 @@ static inline void parlio_ll_enable_bus_clock(int group_id, bool enable)
*
* @param group_id The group id of the parlio module
*/
__attribute__((always_inline))
static inline void parlio_ll_reset_register(int group_id)
{
(void)group_id;
@@ -89,6 +90,7 @@ static inline void parlio_ll_reset_register(int group_id)
* @param dev Parallel IO register base address
* @param src Clock source
*/
__attribute__((always_inline))
static inline void parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
{
(void)dev;
components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h
+2
View File
@@ -92,6 +92,7 @@ static inline void _parlio_ll_enable_bus_clock(int group_id, bool enable)
*
* @param group_id The group id of the parlio module
*/
__attribute__((always_inline))
static inline void _parlio_ll_reset_register(int group_id)
{
(void)group_id;
@@ -114,6 +115,7 @@ static inline void _parlio_ll_reset_register(int group_id)
* @param dev Parallel IO register base address
* @param src Clock source
*/
__attribute__((always_inline))
static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
{
(void)dev;