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change(esp_hal_rtc_timer): unify lp_timer/rtc_timer naming to RTC_TIMER

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This commit is contained in:
wuzhenghui
2026-01-31 22:31:34 +08:00
committed by morris
parent 12b9fb6549
commit 2d8c6ed6b4
88 changed files with 1117 additions and 941 deletions
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components/esp_hw_support/CMakeLists.txt
+2 -2
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@@ -9,9 +9,9 @@ if(${target} STREQUAL "linux")
return()
endif()
set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_rtc_timer)
set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu)
# only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_security)
set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_security esp_hal_rtc_timer)
if(${target} STREQUAL "esp32c6")
list(APPEND priv_requires hal)
components/esp_hw_support/hw_random.c
+5 -12
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,9 +19,7 @@
#include "esp_private/startup_internal.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_hal.h"
#endif
#include "hal/rtc_timer_hal.h"
#if SOC_RNG_CLOCK_IS_INDEPENDENT
#include "hal/lp_clkrst_ll.h"
@@ -74,21 +72,16 @@ uint32_t IRAM_ATTR esp_random(void)
static uint32_t last_ccount = 0;
uint32_t ccount;
uint32_t result = 0;
#if SOC_LP_TIMER_SUPPORTED
for (size_t i = 0; i < sizeof(result); i++) {
do {
ccount = esp_cpu_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
uint32_t current_rtc_timer_counter = (lp_timer_hal_get_cycle_count() & 0xFF);
#if SOC_RTC_TIMER_SUPPORTED
uint32_t current_rtc_timer_counter = (rtc_timer_hal_get_cycle_count(0) & 0xFF);
result ^= (current_rtc_timer_counter << (i * 8));
}
#else
do {
ccount = esp_cpu_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
#endif
}
last_ccount = ccount;
return result ^ REG_READ(WDEV_RND_REG);
}
components/esp_hw_support/include/esp_private/esp_pmu.h
+1 -1
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@@ -73,7 +73,7 @@ typedef enum {
#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN)
#endif
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
#define RTC_TIMER_TRIG_EN PMU_LP_TIMER_WAKEUP_EN //!< Timer wakeup
#else
#define RTC_TIMER_TRIG_EN 0
components/esp_hw_support/port/esp32/rtc_time.c
+2 -2
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@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/rtc.h"
#include "hal/timer_periph.h"
@@ -159,7 +159,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void)
components/esp_hw_support/port/esp32c2/rtc_time.c
+2 -2
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@@ -9,7 +9,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_rom_sys.h"
@@ -170,7 +170,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/port/esp32c3/rtc_time.c
+2 -2
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@@ -9,7 +9,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_rom_sys.h"
@@ -170,7 +170,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/port/esp32c5/rtc_time.c
+2 -2
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@@ -8,7 +8,7 @@
#include "esp32c5/rom/ets_sys.h"
#include "soc/rtc.h"
#include "soc/lp_timer_reg.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -188,7 +188,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32c6/rtc_time.c
+2 -2
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@@ -8,7 +8,7 @@
#include "esp32c6/rom/ets_sys.h"
#include "soc/rtc.h"
#include "soc/pcr_reg.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -231,7 +231,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32c61/rtc_time.c
+2 -2
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@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32c61/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -187,7 +187,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32h2/rtc_time.c
+2 -2
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@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32h2/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -231,7 +231,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32h21/rtc_time.c
+2 -2
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@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32h21/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -205,7 +205,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32h4/rtc_time.c
+2 -2
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@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32h4/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -204,7 +204,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32p4/rtc_time.c
+2 -2
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@@ -8,7 +8,7 @@
#include <assert.h>
#include "esp32p4/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/hp_sys_clkrst_reg.h"
@@ -213,7 +213,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32s2/rtc_time.c
+2 -2
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@@ -9,7 +9,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
@@ -234,7 +234,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/port/esp32s3/rtc_time.c
+2 -2
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@@ -10,7 +10,7 @@
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
@@ -169,7 +169,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/sleep_modes.c
+2 -9
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@@ -139,9 +139,7 @@
#include "soc/pmu_icg_mapping.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_hal.h"
#endif
#include "hal/rtc_timer_hal.h"
#if SOC_VBAT_SUPPORTED
#include "esp_vbat.h"
@@ -1780,7 +1778,6 @@ static SLEEP_FN_ATTR esp_err_t timer_wakeup_prepare(int64_t sleep_duration)
int64_t ticks = rtc_time_us_to_slowclk(sleep_duration, s_config.rtc_clk_cal_period);
int64_t target_wakeup_tick = s_config.rtc_ticks_at_sleep_start + ticks;
#if SOC_LP_TIMER_SUPPORTED
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
int64_t backup_cost_ticks = rtc_time_us_to_slowclk(((pmu_sleep_machine_constant_t *)PMU_instance()->mc)->hp.regdma_a2s_work_time_us, s_config.rtc_clk_cal_period);
// Last timer wake-up validity check
@@ -1790,11 +1787,7 @@ static SLEEP_FN_ATTR esp_err_t timer_wakeup_prepare(int64_t sleep_duration)
return ESP_ERR_SLEEP_REJECT;
}
#endif
lp_timer_hal_set_alarm_target(0, target_wakeup_tick);
#else
rtc_hal_set_wakeup_timer(target_wakeup_tick);
#endif
rtc_timer_hal_set_wakeup_time(0, target_wakeup_tick);
return ESP_OK;
}
components/esp_hw_support/sleep_wake_stub.c
+5 -26
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,17 +18,8 @@
#include "soc/soc_caps.h"
#include "hal/uart_ll.h"
#include "hal/clk_tree_ll.h"
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_ll.h"
#include "hal/lp_timer_hal.h"
#else
#include "hal/rtc_cntl_ll.h"
#endif
#if SOC_PMU_SUPPORTED
#include "hal/pmu_ll.h"
#endif
#include "hal/rtc_hal.h"
#include "hal/rtc_timer_ll.h"
#include "sdkconfig.h"
#include "esp_rom_serial_output.h"
@@ -93,20 +84,8 @@ void RTC_IRAM_ATTR esp_wake_stub_uart_tx_wait_idle(uint8_t uart_no)
void RTC_IRAM_ATTR esp_wake_stub_set_wakeup_time(uint64_t time_in_us)
{
uint64_t rtc_count_delta = time_in_us * (1 << RTC_CLK_CAL_FRACT) / clk_ll_rtc_slow_load_cal();
#if SOC_LP_TIMER_SUPPORTED
lp_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = lp_timer_ll_get_counter_value_low(&LP_TIMER, 0);
uint32_t hi = lp_timer_ll_get_counter_value_high(&LP_TIMER, 0);
uint64_t rtc_curr_count = (uint64_t)hi << 32 | lo;
lp_timer_ll_clear_alarm_intr_status(&LP_TIMER);
lp_timer_ll_set_alarm_target(&LP_TIMER, 0, rtc_curr_count + rtc_count_delta);
lp_timer_ll_set_target_enable(&LP_TIMER, 0, true);
#else
uint64_t rtc_curr_count = rtc_cntl_ll_get_rtc_time();
rtc_cntl_ll_set_wakeup_timer(rtc_curr_count + rtc_count_delta);
#endif
uint64_t rtc_curr_count = rtc_timer_ll_get_cycle_count(0);
rtc_timer_ll_set_wakeup_time(0, rtc_curr_count + rtc_count_delta);
}
uint32_t RTC_IRAM_ATTR esp_wake_stub_get_wakeup_cause(void)
components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
+2 -2
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@@ -243,7 +243,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
printf("PASS. Time measurement...");
}
uint32_t fail_measure = 0;
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
uint64_t clk_rtc_time;
for (int j = 0; j < 3; ++j) {
clk_rtc_time = esp_clk_rtc_time();
@@ -334,7 +334,7 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_
#endif // !defined(CONFIG_IDF_CI_BUILD) || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
#endif // SOC_CLK_XTAL32K_SUPPORTED
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
{
int64_t t1 = esp_rtc_get_time_us();