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feat(esp_tee): Support for ESP32-C61 - the rest of the components

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This commit is contained in:
Laukik Hase
2025-11-19 10:57:42 +05:30
parent 2394e9451d
commit 2cb0fa5c34
16 changed files with 180 additions and 42 deletions
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components/esp_hw_support/port/esp32c61/CMakeLists.txt
+3 -1
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@@ -1,3 +1,5 @@
idf_build_get_property(non_os_build NON_OS_BUILD)
set(srcs "rtc_clk_init.c"
"rtc_clk.c"
"pmu_param.c"
@@ -8,7 +10,7 @@ set(srcs "rtc_clk_init.c"
"ocode_init.c"
)
if(NOT BOOTLOADER_BUILD)
if(NOT non_os_build)
list(APPEND srcs "sar_periph_ctrl.c")
endif()
components/esp_hw_support/port/esp32c61/cpu_region_protect.c
+9
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@@ -123,6 +123,15 @@ void esp_cpu_configure_region_protection(void)
// Configure all the invalid address regions using PMA
//
esp_cpu_configure_invalid_regions();
/* NOTE: When ESP-TEE is active, only configure invalid memory regions in bootloader
* to prevent errors before TEE initialization. TEE will handle all other
* memory protection.
*/
#if CONFIG_SECURE_ENABLE_TEE && BOOTLOADER_BUILD
return;
#endif
//
// Configure all the valid address regions using PMP
//
components/esp_hw_support/port/esp32c61/esp_cpu_intr.c
+15 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,7 +15,20 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
* Reserve interrupt line 1 for the Wifi controller.
* Reserve interrupt line 6 since it is used for disabling interrupts in the interrupt allocator (INT_MUX_DISABLED_INTNO)
*/
const uint32_t rsvd_mask = BIT(1) | BIT(6);
const uint32_t base_rsvd_mask = BIT(1) | BIT(6);
/* On the ESP32-C61, interrupt 31 is reserved for ESP-TEE
* for operations related to secure peripherals under its control
* (e.g. SHA, ECC, APM)
*
* Interrupt 30 is reserved for handling REE interrupts occurring in TEE.
*/
#if CONFIG_SECURE_ENABLE_TEE
const uint32_t rsvd_mask = base_rsvd_mask | BIT(30) | BIT(31);
#else
const uint32_t rsvd_mask = base_rsvd_mask;
#endif
intr_desc_ret->priority = 1;
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);