Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'refactor/fine_tune_dphy_pll_v5.3' into 'release/v5.3'

Browse Source 
feat(mipi): fine tune DPHY PLL clock (v5.3)

See merge request espressif/esp-idf!35292
This commit is contained in:
morris
2024-12-10 11:36:03 +08:00
parent 369befb8fc 6f992acf31
commit 2c9ab21629
4 changed files with 38 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+1 -1
View File
@@ -31,7 +31,7 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
break;
case SOC_MOD_CLK_PLL_F20M:
clk_src_freq = CLK_LL_PLL_20M_FREQ_MHZ * MHZ;
clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ / clk_ll_pll_f20m_get_divider() * MHZ;
break;
case SOC_MOD_CLK_PLL_F80M:
clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;