diff --git a/components/esp_hal_clock/esp32h4/include/hal/clk_gate_ll.h b/components/esp_hal_clock/esp32h4/include/hal/clk_gate_ll.h
index 95c71c48ae7..1325c262c81 100644
--- a/components/esp_hal_clock/esp32h4/include/hal/clk_gate_ll.h
+++ b/components/esp_hal_clock/esp32h4/include/hal/clk_gate_ll.h
@@ -152,13 +152,18 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
         PCR.parl_clk_tx_conf.parl_clk_tx_en = 0;
         PCR.parl_io_conf.parl_clk_en = 0;
         PCR.gdma_conf.gdma_clk_en = 0;
+        PCR.regdma_conf.regdma_clk_en = 0;
 
         if (config->disable_mspi_flash_clk) {
             PCR.mspi_conf.mspi_clk_en = 0;
+            PCR.mspi_conf.mspi_pll_clk_en = 0;
+            PCR.mspi_clk_conf.mspi_func_clk_en = 0;
         }
 
         PCR.spi2_conf.spi2_clk_en = 0;
+        PCR.spi2_clkm_conf.spi2_clkm_en = 0;
         PCR.spi3_conf.spi3_clk_en = 0;
+        PCR.spi3_clkm_conf.spi3_clkm_en = 0;
         PCR.tsens_clk_conf.tsens_clk_en = 0;
 
         PCR.uhci_conf.uhci_clk_en = 0;
@@ -172,6 +177,7 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
             /* Disable ASSIST Debug module clock if PC recording is not used;
              * stack guard may re-enable in esp_hw_stack_guard_init */
             PCR.assist_conf.assist_clk_en = 0;
+            PCR.assist_conf.assist1_clk_en = 0;
         }
 
         if (config->disable_crypto_periph_clk) {
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
index 73a0251ad12..8f705317295 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
@@ -623,6 +623,7 @@ TEST_CASE("allocate 2 handlers for a same source and remove the later one", "[in
 
     // enable SPI2
     PERIPH_RCC_ATOMIC() {
+        spi_ll_enable_clock(1, true);
         spi_ll_enable_bus_clock(1, true);
         spi_ll_reset_register(1);
     }