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feat(mipi): fine tune DPHY PLL clock

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morris
2024-11-28 11:20:45 +08:00
parent e0af9f104a
commit 2bf02443f1
4 changed files with 39 additions and 12 deletions
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components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+1 -1
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@@ -33,7 +33,7 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
break;
case SOC_MOD_CLK_PLL_F20M:
clk_src_freq = CLK_LL_PLL_20M_FREQ_MHZ * MHZ;
clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ / clk_ll_pll_f20m_get_divider() * MHZ;
break;
case SOC_MOD_CLK_PLL_F80M:
clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;