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feat(mmu): s31 support
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -97,10 +97,12 @@ extern "C" {
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* MMU Linear Address
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*----------------------------------------------------------------------------*/
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/**
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* - 64KB MMU page size: the last 0xFFFF, which is the offset
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* - 1024 MMU entries for flash, 1024 MMU entries for psram, needs 0xFFF to hold it.
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* - 64KB MMU page size: the lower 0xFFFF bits are the page offset
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* - Flash linear addresses start from 0x00000000, PSRAM linear addresses start from 0x08000000
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* - The mask keeps the bits needed to distinguish flash and PSRAM linear ranges while discarding
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* the upper virtual-address tag bits
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*
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* Therefore, 0x3F,FFFF
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* Therefore, use 0x0FFFFFFF.
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*/
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#define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFFFF
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