refactor(clk): add soc_clk_calibration_clk_src_t for all targets

Cleaned up RTC calibration clock selection code

components/soc/esp32/include/soc/clk_tree_defs.h

@@ -484,6 +484,16 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RTC_SLOW,                                /*!< Select to calibrate RTC_SLOW_CLK */
+    CLK_CAL_RC_FAST_D256,                            /*!< Select to calibrate RC_FAST_D256_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32/register/soc/timer_group_struct.h

@@ -347,7 +347,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling: 1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
-         *  0:rtcslowclock. 1:clk_80m.  2:xtal_32k.
+         *  0:rtc_slow_clock. 1:rc_fast_div_clk.  2:xtal_32k.
          */
         uint32_t rtc_cali_clk_sel: 2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

components/soc/esp32c2/include/soc/clk_tree_defs.h

@@ -325,6 +325,16 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC_FAST_D256,                            /*!< Select to calibrate RC_FAST_D256_CLK */
+    CLK_CAL_32K_OSC_SLOW,                            /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c2/register/soc/timer_group_struct.h

@@ -335,7 +335,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling:1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         *  0:rc_slow_clk. 1:rc_fast_div_clk, 2:32k_osc_slow_clk.
          */
         uint32_t rtc_cali_clk_sel:2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

components/soc/esp32c3/include/soc/clk_tree_defs.h

@@ -394,6 +394,16 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC_FAST_D256,                            /*!< Select to calibrate RC_FAST_D256_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c3/register/soc/timer_group_struct.h

@@ -339,7 +339,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling: 1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         *  0:rc_slow_clk. 1:rc_fast_div_clk.  2:xtal_32k.
          */
         uint32_t rtc_cali_clk_sel: 2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

components/soc/esp32c5/include/soc/clk_tree_defs.h

@@ -558,6 +558,17 @@ typedef enum {
     CLKOUT_SIG_RC_SLOW          = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+    CLK_CAL_32K_OSC_SLOW,                            /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
+    CLK_CAL_RC_FAST,                                 /*!< Select to calibrate RC_FAST_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -516,6 +516,18 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC32K,                                   /*!< Select to calibrate RC32K_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+    CLK_CAL_32K_OSC_SLOW,                            /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
+    CLK_CAL_RC_FAST,                                 /*!< Select to calibrate RC_FAST_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c6/register/soc/timer_group_struct.h

@@ -339,7 +339,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling:1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         *  0/3:rc_slow_clk. 1:rc_fast_div_clk, 2:32k clock, which 32k depends on PCR.ctrl_32k_conf.clk_32k_sel.
          */
         uint32_t rtc_cali_clk_sel:2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

components/soc/esp32c61/include/soc/clk_tree_defs.h

@@ -396,6 +396,17 @@ typedef enum {
     CLKOUT_SIG_RC_SLOW          = 0x19, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+    CLK_CAL_32K_OSC_SLOW,                            /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
+    CLK_CAL_RC_FAST,                                 /*!< Select to calibrate RC_FAST_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -525,6 +525,18 @@ typedef enum {
     CLKOUT_SIG_INVALID = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC32K,                                   /*!< Select to calibrate RC32K_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+    CLK_CAL_32K_OSC_SLOW,                            /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
+    CLK_CAL_RC_FAST,                                 /*!< Select to calibrate RC_FAST_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/register/soc/timer_group_struct.h

@@ -339,7 +339,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling:1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         *  0/3:rc_slow_clk. 1:rc_fast_div_clk, 2:32k clock, which 32k depends on PCR.ctrl_32k_conf.clk_32k_sel.
          */
         uint32_t rtc_cali_clk_sel:2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

components/soc/esp32h21/include/soc/clk_tree_defs.h

@@ -347,7 +347,7 @@ typedef enum {
     CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
     CLK_CAL_32K_OSC_SLOW,                            /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
     CLK_CAL_RC_FAST,                                 /*!< Select to calibrate RC_FAST_CLK */
-} soc_clk_calibration_clk_src_t;
+} soc_timg0_calibration_clk_src_t;
 
 #ifdef __cplusplus
 }

components/soc/esp32h21/register/soc/timer_group_struct.h

@@ -339,7 +339,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling:1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         *  0:rc_slow_clk. 1:rc_fast_clk, 2:32k clk.
          */
         uint32_t rtc_cali_clk_sel:2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

components/soc/esp32h4/include/soc/clk_tree_defs.h

@@ -306,7 +306,7 @@ typedef enum {
     CLK_CAL_GPSPI3_MST,                              /*!< Select to calibrate GPSPI3_MST_CLK */
     CLK_CAL_GPSPI2_MST,                              /*!< Select to calibrate GPSPI2_MST_CLK */
     CLK_CAL_EXT_IO,                                  /*!< Select to calibrate an external clock from an IO */
-} soc_clk_calibration_clk_src_t;
+} soc_timg0_calibration_clk_src_t;
 /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -797,6 +797,25 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_MPLL = 0,                                /*!< Select to calibrate MPLL_CLK */
+    CLK_CAL_SPLL,                                    /*!< Select to calibrate SPLL_CLK */
+    CLK_CAL_CPLL,                                    /*!< Select to calibrate CPLL_CLK */
+    CLK_CAL_APLL,                                    /*!< Select to calibrate APLL_CLK */
+    CLK_CAL_SDIO_PLL0,                               /*!< Select to calibrate SDIO_PLL0_CLK */
+    CLK_CAL_SDIO_PLL1,                               /*!< Select to calibrate SDIO_PLL1_CLK */
+    CLK_CAL_SDIO_PLL2,                               /*!< Select to calibrate SDIO_PLL2_CLK */
+    CLK_CAL_RC_FAST,                                 /*!< Select to calibrate RC_FAST_CLK */
+    CLK_CAL_RC_SLOW,                                 /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC32K,                                   /*!< Select to calibrate RC32K_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+    CLK_CAL_LP_PLL,                                  /*!< Select to calibrate LP_PLL_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s2/include/soc/clk_tree_defs.h

@@ -454,6 +454,16 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC_FAST_D256,                            /*!< Select to calibrate RC_FAST_D256_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s2/register/soc/timer_group_struct.h

@@ -360,7 +360,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling: 1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
-         *  0:rtcslowclock. 1:clk_80m.  2:xtal_32k.
+         *  0:rc_slow_clk. 1:rc_fast_div_clk.  2:xtal_32k.
          */
         uint32_t rtc_cali_clk_sel: 2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;

components/soc/esp32s3/include/soc/clk_tree_defs.h

@@ -499,6 +499,16 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC_FAST_D256,                            /*!< Select to calibrate RC_FAST_D256_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s3/register/soc/timer_group_struct.h

@@ -328,7 +328,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling: 1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
-         *  0:rtc slow clock. 1:clk_80m.  2:xtal_32k.
+         *  0:rc_slow_clk. 1:rc_fast_div_clk.  2:xtal_32k.
          */
         uint32_t rtc_cali_clk_sel: 2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;