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refactor(clk): add soc_clk_calibration_clk_src_t for all targets

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Cleaned up RTC calibration clock selection code
This commit is contained in:
Song Ruo Jing
2025-07-30 20:01:46 +08:00
parent 07120c1d38
commit 2b01b7c6f8
54 changed files with 786 additions and 495 deletions
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components/hal/esp32h21/include/hal/clk_tree_ll.h
+10 -10
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@@ -413,9 +413,9 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
/**
* @brief Select the calibration clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_clk_calibration_clk_src_t
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_clk_calibration_clk_src_t clk_sel)
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
int clk_32k_sel = -1;
@@ -448,6 +448,14 @@ static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(
}
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/**
* @brief Select the clock source for RTC_SLOW_CLK
*
@@ -551,14 +559,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider
return 1;
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_tick_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/**
* @brief Set RC_SLOW_CLK divider. The output from the divider is passed into rtc_slow_clk MUX.
*