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fix(spi_flash): Fix suspend issue on esp32s31, and add trs timing on other target

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C.S.M
2026-06-08 11:15:13 +08:00
parent cd9de8284d
commit 2acd9b9a7c
26 changed files with 249 additions and 46 deletions
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components/esp_hal_mspi/esp32c5/include/hal/spimem_flash_ll.h
+18 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -226,6 +226,23 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
dev->sus_status.flash_pes_dly_128 = 1;
}
/**
* @brief Get trs unit values in SPI_CLK cycles
*
* @param dev Beginning address of the peripheral registers.
* @return uint32_t trs unit values
*/
static inline uint32_t spimem_flash_ll_get_trs_unit_in_cycles(spi_mem_dev_t *dev)
{
uint32_t trs_unit = 0;
if (dev->sus_status.flash_per_dly_128 == 1) {
trs_unit = 128;
} else {
trs_unit = 4;
}
return trs_unit;
}
/**
* Configure the delay after Resume
*
@@ -235,7 +252,6 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val)
{
dev->ctrl1.cs_hold_dly_per = dly_val;
dev->sus_status.flash_per_dly_128 = 1;
}
/**