mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
feat: enabled ECDSA peripheral support for ESSP32-P4
This commit is contained in:
nilesh.kale
@@ -213,7 +213,7 @@ config SOC_ECC_EXTENDED_MODES_SUPPORTED
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config SOC_ECDSA_SUPPORTED
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bool
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default n
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default y
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config SOC_KEY_MANAGER_SUPPORTED
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bool
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@@ -1335,10 +1335,22 @@ config SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
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bool
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default y
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config SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP
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bool
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default y
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config SOC_ECDSA_USES_MPI
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bool
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default y
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config SOC_ECDSA_SUPPORT_CURVE_P384
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bool
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default y
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config SOC_ECDSA_SUPPORT_CURVE_SPECIFIC_KEY_PURPOSES
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bool
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default y
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config SOC_SPI_PERIPH_NUM
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int
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default 3
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@@ -1611,13 +1623,21 @@ config SOC_EFUSE_XTS_AES_KEY_256
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bool
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default y
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config SOC_EFUSE_ECDSA_KEY_P192
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bool
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default y
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config SOC_EFUSE_ECDSA_KEY_P384
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bool
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default y
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config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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bool
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default y
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config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
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bool
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default n
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default y
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config SOC_KEY_MANAGER_FE_KEY_DEPLOY
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bool
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -75,7 +75,7 @@
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#define SOC_DIG_SIGN_SUPPORTED 1
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#define SOC_ECC_SUPPORTED 1
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#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
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#define SOC_ECDSA_SUPPORTED 0 // TODO: IDF-13523
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#define SOC_ECDSA_SUPPORTED 1
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#define SOC_KEY_MANAGER_SUPPORTED 1
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#define SOC_HUK_SUPPORTED 1
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#define SOC_FLASH_ENC_SUPPORTED 1
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@@ -513,7 +513,10 @@
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/*--------------------------- ECDSA CAPS ---------------------------------------*/
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#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
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#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1)
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#define SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP (1)
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#define SOC_ECDSA_USES_MPI (1)
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#define SOC_ECDSA_SUPPORT_CURVE_P384 (1)
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#define SOC_ECDSA_SUPPORT_CURVE_SPECIFIC_KEY_PURPOSES (1) /*!< Support individual key purposes for different ECDSA curves (P192, P256, P384) */
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 3
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@@ -614,13 +617,16 @@
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#define SOC_EFUSE_SOFT_DIS_JTAG 1
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/* Capability to disable the MSPI access in download mode */
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#define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1
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// ECDSA_P256_KEY
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#define SOC_EFUSE_ECDSA_KEY 1
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#define SOC_EFUSE_XTS_AES_KEY_128 1
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#define SOC_EFUSE_XTS_AES_KEY_256 1
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#define SOC_EFUSE_ECDSA_KEY_P192 1
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#define SOC_EFUSE_ECDSA_KEY_P384 1
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/*-------------------------- Key Manager CAPS----------------------------*/
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#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */
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#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 0 /*!< Key manager responsible to deploy ECDSA key */ // TODO: IDF-13523
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#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 1 /*!< Key manager responsible to deploy the XTS-AES-128 key */
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#define SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 1 /*!< Key manager responsible to deploy the XTS-AES-256 key */
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@@ -1,359 +0,0 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** ECDSA_CONF_REG register
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* ECDSA configure register
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*/
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#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
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/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
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* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
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* Generate Mode. 2: Export Public Key Mode. 3: invalid.
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*/
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#define ECDSA_WORK_MODE 0x00000003U
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#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
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#define ECDSA_WORK_MODE_V 0x00000003U
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#define ECDSA_WORK_MODE_S 0
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/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
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* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384.
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*/
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#define ECDSA_ECC_CURVE 0x00000003U
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#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
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#define ECDSA_ECC_CURVE_V 0x00000003U
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#define ECDSA_ECC_CURVE_S 2
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/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
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* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
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* written by software.
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*/
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#define ECDSA_SOFTWARE_SET_K (BIT(4))
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#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
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#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
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#define ECDSA_SOFTWARE_SET_K_S 4
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/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
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* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
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* software.
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*/
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#define ECDSA_SOFTWARE_SET_Z (BIT(5))
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#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
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#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
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#define ECDSA_SOFTWARE_SET_Z_S 5
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/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
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* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
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* deterministic derivation algorithm.
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*/
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#define ECDSA_DETERMINISTIC_K (BIT(6))
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#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
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#define ECDSA_DETERMINISTIC_K_V 0x00000001U
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#define ECDSA_DETERMINISTIC_K_S 6
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/** ECDSA_CLK_REG register
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* ECDSA clock gate register
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*/
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#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
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/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
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* Write 1 to force on register clock gate.
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*/
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#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
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#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
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#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
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#define ECDSA_CLK_GATE_FORCE_ON_S 0
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/** ECDSA_INT_RAW_REG register
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* ECDSA interrupt raw register, valid in level.
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*/
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#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
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/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
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*/
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#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
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#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
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#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
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#define ECDSA_PREP_DONE_INT_RAW_S 0
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/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
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*/
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#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
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#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
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#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
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#define ECDSA_PROC_DONE_INT_RAW_S 1
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/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the ecdsa_post_done_int interrupt
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*/
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#define ECDSA_POST_DONE_INT_RAW (BIT(2))
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#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
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#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
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#define ECDSA_POST_DONE_INT_RAW_S 2
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/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
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* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
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#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
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#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_RAW_S 3
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/** ECDSA_INT_ST_REG register
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* ECDSA interrupt status register.
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*/
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#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
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/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
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*/
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#define ECDSA_PREP_DONE_INT_ST (BIT(0))
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#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
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#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
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#define ECDSA_PREP_DONE_INT_ST_S 0
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/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
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*/
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#define ECDSA_PROC_DONE_INT_ST (BIT(1))
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#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
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#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
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#define ECDSA_PROC_DONE_INT_ST_S 1
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/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
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* The masked interrupt status bit for the ecdsa_post_done_int interrupt
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*/
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#define ECDSA_POST_DONE_INT_ST (BIT(2))
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#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
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#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
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#define ECDSA_POST_DONE_INT_ST_S 2
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/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
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* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
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#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
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#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_ST_S 3
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/** ECDSA_INT_ENA_REG register
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* ECDSA interrupt enable register.
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*/
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#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
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/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the ecdsa_prep_done_int interrupt
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*/
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#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
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#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
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#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
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#define ECDSA_PREP_DONE_INT_ENA_S 0
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/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the ecdsa_proc_done_int interrupt
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*/
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#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
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#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
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#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
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#define ECDSA_PROC_DONE_INT_ENA_S 1
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/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
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* The interrupt enable bit for the ecdsa_post_done_int interrupt
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*/
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#define ECDSA_POST_DONE_INT_ENA (BIT(2))
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#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
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#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
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#define ECDSA_POST_DONE_INT_ENA_S 2
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/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
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* The interrupt enable bit for the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
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#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
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#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_ENA_S 3
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/** ECDSA_INT_CLR_REG register
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* ECDSA interrupt clear register.
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*/
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#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
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/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the ecdsa_prep_done_int interrupt
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*/
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#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
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#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
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#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
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#define ECDSA_PREP_DONE_INT_CLR_S 0
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/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the ecdsa_proc_done_int interrupt
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*/
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#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
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#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
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#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
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#define ECDSA_PROC_DONE_INT_CLR_S 1
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/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the ecdsa_post_done_int interrupt
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*/
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#define ECDSA_POST_DONE_INT_CLR (BIT(2))
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#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
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#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
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#define ECDSA_POST_DONE_INT_CLR_S 2
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/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
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* Set this bit to clear the ecdsa_sha_release_int interrupt
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*/
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#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
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#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
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#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
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#define ECDSA_SHA_RELEASE_INT_CLR_S 3
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/** ECDSA_START_REG register
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* ECDSA start register
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*/
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#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
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/** ECDSA_START : WT; bitpos: [0]; default: 0;
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* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
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* after configuration.
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*/
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#define ECDSA_START (BIT(0))
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#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
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#define ECDSA_START_V 0x00000001U
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#define ECDSA_START_S 0
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/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
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* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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#define ECDSA_LOAD_DONE (BIT(1))
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#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
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#define ECDSA_LOAD_DONE_V 0x00000001U
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#define ECDSA_LOAD_DONE_S 1
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/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
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* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
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* self-cleared after configuration.
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*/
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#define ECDSA_GET_DONE (BIT(2))
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#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
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#define ECDSA_GET_DONE_V 0x00000001U
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#define ECDSA_GET_DONE_S 2
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/** ECDSA_STATE_REG register
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* ECDSA status register
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*/
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#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
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/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
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* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
|
||||
* state.
|
||||
*/
|
||||
#define ECDSA_BUSY 0x00000003U
|
||||
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
|
||||
#define ECDSA_BUSY_V 0x00000003U
|
||||
#define ECDSA_BUSY_S 0
|
||||
|
||||
/** ECDSA_RESULT_REG register
|
||||
* ECDSA result register
|
||||
*/
|
||||
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
|
||||
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
|
||||
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
|
||||
* done.
|
||||
*/
|
||||
#define ECDSA_OPERATION_RESULT (BIT(0))
|
||||
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
|
||||
#define ECDSA_OPERATION_RESULT_V 0x00000001U
|
||||
#define ECDSA_OPERATION_RESULT_S 0
|
||||
|
||||
/** ECDSA_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
|
||||
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984;
|
||||
* ECDSA version control register
|
||||
*/
|
||||
#define ECDSA_DATE 0x0FFFFFFFU
|
||||
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
|
||||
#define ECDSA_DATE_V 0x0FFFFFFFU
|
||||
#define ECDSA_DATE_S 0
|
||||
|
||||
/** ECDSA_SHA_MODE_REG register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
|
||||
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
|
||||
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
|
||||
*/
|
||||
#define ECDSA_SHA_MODE 0x00000007U
|
||||
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
|
||||
#define ECDSA_SHA_MODE_V 0x00000007U
|
||||
#define ECDSA_SHA_MODE_S 0
|
||||
|
||||
/** ECDSA_SHA_START_REG register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
|
||||
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
#define ECDSA_SHA_START (BIT(0))
|
||||
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
|
||||
#define ECDSA_SHA_START_V 0x00000001U
|
||||
#define ECDSA_SHA_START_S 0
|
||||
|
||||
/** ECDSA_SHA_CONTINUE_REG register
|
||||
* ECDSA control SHA register
|
||||
*/
|
||||
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
|
||||
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
|
||||
* bit will be self-cleared after configuration.
|
||||
*/
|
||||
#define ECDSA_SHA_CONTINUE (BIT(0))
|
||||
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
|
||||
#define ECDSA_SHA_CONTINUE_V 0x00000001U
|
||||
#define ECDSA_SHA_CONTINUE_S 0
|
||||
|
||||
/** ECDSA_SHA_BUSY_REG register
|
||||
* ECDSA status register
|
||||
*/
|
||||
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
|
||||
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
|
||||
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
|
||||
* calculation. 0: SHA is idle.
|
||||
*/
|
||||
#define ECDSA_SHA_BUSY (BIT(0))
|
||||
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
|
||||
#define ECDSA_SHA_BUSY_V 0x00000001U
|
||||
#define ECDSA_SHA_BUSY_S 0
|
||||
|
||||
/** ECDSA_MESSAGE_MEM register
|
||||
* The memory that stores message.
|
||||
*/
|
||||
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
|
||||
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
|
||||
|
||||
/** ECDSA_R_MEM register
|
||||
* The memory that stores r.
|
||||
*/
|
||||
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
|
||||
#define ECDSA_R_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_S_MEM register
|
||||
* The memory that stores s.
|
||||
*/
|
||||
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
|
||||
#define ECDSA_S_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_Z_MEM register
|
||||
* The memory that stores software written z.
|
||||
*/
|
||||
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
|
||||
#define ECDSA_Z_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_QAX_MEM register
|
||||
* The memory that stores x coordinates of QA or software written k.
|
||||
*/
|
||||
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
|
||||
#define ECDSA_QAX_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_QAY_MEM register
|
||||
* The memory that stores y coordinates of QA.
|
||||
*/
|
||||
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
|
||||
#define ECDSA_QAY_MEM_SIZE_BYTES 48
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -23,44 +23,37 @@ extern "C" {
|
||||
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
|
||||
#define ECDSA_WORK_MODE_V 0x00000003U
|
||||
#define ECDSA_WORK_MODE_S 0
|
||||
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
|
||||
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
|
||||
/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
|
||||
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384.
|
||||
*/
|
||||
#define ECDSA_ECC_CURVE (BIT(2))
|
||||
#define ECDSA_ECC_CURVE 0x00000003U
|
||||
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
|
||||
#define ECDSA_ECC_CURVE_V 0x00000001U
|
||||
#define ECDSA_ECC_CURVE_V 0x00000003U
|
||||
#define ECDSA_ECC_CURVE_S 2
|
||||
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
|
||||
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
|
||||
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
|
||||
* written by software.
|
||||
*/
|
||||
#define ECDSA_SOFTWARE_SET_K (BIT(3))
|
||||
#define ECDSA_SOFTWARE_SET_K (BIT(4))
|
||||
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
|
||||
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
|
||||
#define ECDSA_SOFTWARE_SET_K_S 3
|
||||
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
|
||||
#define ECDSA_SOFTWARE_SET_K_S 4
|
||||
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
|
||||
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
|
||||
* software.
|
||||
*/
|
||||
#define ECDSA_SOFTWARE_SET_Z (BIT(4))
|
||||
#define ECDSA_SOFTWARE_SET_Z (BIT(5))
|
||||
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
|
||||
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
|
||||
#define ECDSA_SOFTWARE_SET_Z_S 4
|
||||
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
|
||||
#define ECDSA_SOFTWARE_SET_Z_S 5
|
||||
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
|
||||
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
|
||||
* deterministic derivation algorithm.
|
||||
*/
|
||||
#define ECDSA_DETERMINISTIC_K (BIT(5))
|
||||
#define ECDSA_DETERMINISTIC_K (BIT(6))
|
||||
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
|
||||
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
|
||||
#define ECDSA_DETERMINISTIC_K_S 5
|
||||
/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
|
||||
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
|
||||
*/
|
||||
#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
|
||||
#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
|
||||
#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
|
||||
#define ECDSA_DETERMINISTIC_LOOP_S 6
|
||||
#define ECDSA_DETERMINISTIC_K_S 6
|
||||
|
||||
/** ECDSA_CLK_REG register
|
||||
* ECDSA clock gate register
|
||||
@@ -78,77 +71,133 @@ extern "C" {
|
||||
* ECDSA interrupt raw register, valid in level.
|
||||
*/
|
||||
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
|
||||
/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_RAW (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
|
||||
#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_RAW_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
|
||||
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_RAW_S 0
|
||||
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
|
||||
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_RAW_S 1
|
||||
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
|
||||
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_RAW_S 2
|
||||
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
|
||||
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_S 1
|
||||
#define ECDSA_SHA_RELEASE_INT_RAW_S 3
|
||||
|
||||
/** ECDSA_INT_ST_REG register
|
||||
* ECDSA interrupt status register.
|
||||
*/
|
||||
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
|
||||
/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
|
||||
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_ST (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
|
||||
#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_ST_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
|
||||
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_ST_S 0
|
||||
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
|
||||
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_ST_S 1
|
||||
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_POST_DONE_INT_ST (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
|
||||
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_ST_S 2
|
||||
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
|
||||
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_ST (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_S 1
|
||||
#define ECDSA_SHA_RELEASE_INT_ST_S 3
|
||||
|
||||
/** ECDSA_INT_ENA_REG register
|
||||
* ECDSA interrupt enable register.
|
||||
*/
|
||||
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
|
||||
/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
|
||||
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_ENA (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
|
||||
#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_ENA_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
|
||||
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_ENA_S 0
|
||||
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
|
||||
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_ENA_S 1
|
||||
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
|
||||
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_ENA_S 2
|
||||
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
|
||||
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_S 1
|
||||
#define ECDSA_SHA_RELEASE_INT_ENA_S 3
|
||||
|
||||
/** ECDSA_INT_CLR_REG register
|
||||
* ECDSA interrupt clear register.
|
||||
*/
|
||||
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
|
||||
/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_calc_done_int interrupt
|
||||
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the ecdsa_prep_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_CALC_DONE_INT_CLR (BIT(0))
|
||||
#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
|
||||
#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_CALC_DONE_INT_CLR_S 0
|
||||
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
|
||||
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
|
||||
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_PREP_DONE_INT_CLR_S 0
|
||||
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the ecdsa_proc_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
|
||||
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
|
||||
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_PROC_DONE_INT_CLR_S 1
|
||||
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the ecdsa_post_done_int interrupt
|
||||
*/
|
||||
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
|
||||
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
|
||||
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_POST_DONE_INT_CLR_S 2
|
||||
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the ecdsa_sha_release_int interrupt
|
||||
*/
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1))
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_S 1
|
||||
#define ECDSA_SHA_RELEASE_INT_CLR_S 3
|
||||
|
||||
/** ECDSA_START_REG register
|
||||
* ECDSA start register
|
||||
@@ -204,20 +253,12 @@ extern "C" {
|
||||
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
|
||||
#define ECDSA_OPERATION_RESULT_V 0x00000001U
|
||||
#define ECDSA_OPERATION_RESULT_S 0
|
||||
/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
|
||||
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
|
||||
* curve order, then actually taken k = k mod n.
|
||||
*/
|
||||
#define ECDSA_K_VALUE_WARNING (BIT(1))
|
||||
#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
|
||||
#define ECDSA_K_VALUE_WARNING_V 0x00000001U
|
||||
#define ECDSA_K_VALUE_WARNING_S 1
|
||||
|
||||
/** ECDSA_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
|
||||
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
|
||||
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984;
|
||||
* ECDSA version control register
|
||||
*/
|
||||
#define ECDSA_DATE 0x0FFFFFFFU
|
||||
@@ -230,8 +271,8 @@ extern "C" {
|
||||
*/
|
||||
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
|
||||
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
|
||||
* Others: invalid.
|
||||
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
|
||||
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
|
||||
*/
|
||||
#define ECDSA_SHA_MODE 0x00000007U
|
||||
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
|
||||
@@ -281,37 +322,37 @@ extern "C" {
|
||||
* The memory that stores message.
|
||||
*/
|
||||
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
|
||||
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
|
||||
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
|
||||
|
||||
/** ECDSA_R_MEM register
|
||||
* The memory that stores r.
|
||||
*/
|
||||
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
|
||||
#define ECDSA_R_MEM_SIZE_BYTES 32
|
||||
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
|
||||
#define ECDSA_R_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_S_MEM register
|
||||
* The memory that stores s.
|
||||
*/
|
||||
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
|
||||
#define ECDSA_S_MEM_SIZE_BYTES 32
|
||||
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
|
||||
#define ECDSA_S_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_Z_MEM register
|
||||
* The memory that stores software written z.
|
||||
*/
|
||||
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
|
||||
#define ECDSA_Z_MEM_SIZE_BYTES 32
|
||||
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
|
||||
#define ECDSA_Z_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_QAX_MEM register
|
||||
* The memory that stores x coordinates of QA or software written k.
|
||||
*/
|
||||
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
|
||||
#define ECDSA_QAX_MEM_SIZE_BYTES 32
|
||||
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
|
||||
#define ECDSA_QAX_MEM_SIZE_BYTES 48
|
||||
|
||||
/** ECDSA_QAY_MEM register
|
||||
* The memory that stores y coordinates of QA.
|
||||
*/
|
||||
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
|
||||
#define ECDSA_QAY_MEM_SIZE_BYTES 32
|
||||
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
|
||||
#define ECDSA_QAY_MEM_SIZE_BYTES 48
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user