From ca892b17b9827979937022fe5a3b9b8e0af9b1d1 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 18 Nov 2025 11:38:48 +0800 Subject: [PATCH] feat(gpio): support fast gpio driver on esp32h4 --- .../test_apps/gpio_extensions/README.md | 4 +- .../main/test_dedicated_gpio.c | 2 + .../esp32h4/include/hal/dedic_gpio_cpu_ll.h | 58 ++++++++++++++++++ .../include/hal/gpio_glitch_filter_ll.h | 60 +++++++++++++++++++ components/soc/esp32h4/dedic_gpio_periph.c | 58 ++++++++++++++++++ .../esp32h4/include/soc/Kconfig.soc_caps.in | 12 ++++ .../soc/esp32h4/include/soc/clk_tree_defs.h | 17 ++++++ components/soc/esp32h4/include/soc/soc_caps.h | 6 +- .../soc/esp32h4/include/soc/soc_caps_full.h | 4 ++ .../esp32h4/register/soc/gpio_ext_struct.h | 16 ++--- docs/docs_not_updated/esp32h4.txt | 16 ----- .../api-reference/peripherals/dedic_gpio.rst | 2 +- .../api-reference/peripherals/dedic_gpio.rst | 2 +- .../dedicated_gpio/soft_i2c/README.md | 4 +- .../dedicated_gpio/soft_spi/README.md | 4 +- .../dedicated_gpio/soft_uart/README.md | 4 +- 16 files changed, 232 insertions(+), 37 deletions(-) create mode 100644 components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h create mode 100644 components/hal/esp32h4/include/hal/gpio_glitch_filter_ll.h create mode 100644 components/soc/esp32h4/dedic_gpio_periph.c diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/README.md b/components/esp_driver_gpio/test_apps/gpio_extensions/README.md index cc9654f2959..71274ac6dd3 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/README.md +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c index 7f8f5362c07..f0e0d0e1227 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c @@ -136,6 +136,8 @@ TEST_CASE("Dedicated_GPIO_run_on_multiple_CPU_cores", "[dedic_gpio]") for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { #if CONFIG_IDF_TARGET_ESP32P4 int start_gpio = i * TEST_GPIO_GROUP_SIZE + 20; +#elif CONFIG_IDF_TARGET_ESP32H4 + int start_gpio = i * TEST_GPIO_GROUP_SIZE + 13; #else int start_gpio = i * TEST_GPIO_GROUP_SIZE; #endif diff --git a/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h new file mode 100644 index 00000000000..281fbb4704d --- /dev/null +++ b/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "riscv/csr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*fast gpio*/ +#define CSR_GPIO_OEN_USER 0x803 +#define CSR_GPIO_IN_USER 0x804 +#define CSR_GPIO_OUT_USER 0x805 + +/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE 1 + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) +{ + RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); +} + +static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) +{ + RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_in(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); + return value; +} + +__attribute__((always_inline)) +static inline uint32_t dedic_gpio_cpu_ll_read_out(void) +{ + uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); + return value; +} + +__attribute__((always_inline)) +static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) +{ + RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); + RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/include/hal/gpio_glitch_filter_ll.h b/components/hal/esp32h4/include/hal/gpio_glitch_filter_ll.h new file mode 100644 index 00000000000..69944fc0d30 --- /dev/null +++ b/components/hal/esp32h4/include/hal/gpio_glitch_filter_ll.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/assert.h" +#include "soc/gpio_ext_struct.h" + +#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW 64 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable GPIO glitch filter + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_glitch_filter_enable(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, bool enable) +{ + hw->glitch_filter_chn[filter_idx].ext_filter_chn_en = enable; +} + +/** + * @brief Set the input GPIO for the glitch filter + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param gpio_num GPIO number + */ +static inline void gpio_ll_glitch_filter_set_gpio(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t gpio_num) +{ + hw->glitch_filter_chn[filter_idx].ext_filter_chn_input_io_num = gpio_num; +} + +/** + * @brief Set the coefficient of the glitch filter window + * + * @param hw Glitch filter register base address + * @param filter_idx Glitch filter index + * @param window_width Window width, in IOMUX clock ticks + * @param window_threshold Window threshold, in IOMUX clock ticks + */ +static inline void gpio_ll_glitch_filter_set_window_coeff(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t window_width, uint32_t window_thres) +{ + HAL_ASSERT(window_thres <= window_width); + hw->glitch_filter_chn[filter_idx].ext_filter_chn_window_width = window_width - 1; + hw->glitch_filter_chn[filter_idx].ext_filter_chn_window_thres = window_thres - 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/dedic_gpio_periph.c b/components/soc/esp32h4/dedic_gpio_periph.c new file mode 100644 index 00000000000..f4c3768739e --- /dev/null +++ b/components/soc/esp32h4/dedic_gpio_periph.c @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/gpio_sig_map.h" +#include "soc/dedic_gpio_periph.h" + +const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { + .irq = -1, + .cores = { + [0] = { + .in_sig_per_channel = { + [0] = CPU0_GPIO_IN0_IDX, + [1] = CPU0_GPIO_IN1_IDX, + [2] = CPU0_GPIO_IN2_IDX, + [3] = CPU0_GPIO_IN3_IDX, + [4] = CPU0_GPIO_IN4_IDX, + [5] = CPU0_GPIO_IN5_IDX, + [6] = CPU0_GPIO_IN6_IDX, + [7] = CPU0_GPIO_IN7_IDX, + }, + .out_sig_per_channel = { + [0] = CPU0_GPIO_OUT0_IDX, + [1] = CPU0_GPIO_OUT1_IDX, + [2] = CPU0_GPIO_OUT2_IDX, + [3] = CPU0_GPIO_OUT3_IDX, + [4] = CPU0_GPIO_OUT4_IDX, + [5] = CPU0_GPIO_OUT5_IDX, + [6] = CPU0_GPIO_OUT6_IDX, + [7] = CPU0_GPIO_OUT7_IDX, + } + }, + [1] = { + .in_sig_per_channel = { + [0] = CPU1_GPIO_IN0_IDX, + [1] = CPU1_GPIO_IN1_IDX, + [2] = CPU1_GPIO_IN2_IDX, + [3] = CPU1_GPIO_IN3_IDX, + [4] = CPU1_GPIO_IN4_IDX, + [5] = CPU1_GPIO_IN5_IDX, + [6] = CPU1_GPIO_IN6_IDX, + [7] = CPU1_GPIO_IN7_IDX, + }, + .out_sig_per_channel = { + [0] = CPU1_GPIO_OUT0_IDX, + [1] = CPU1_GPIO_OUT1_IDX, + [2] = CPU1_GPIO_OUT2_IDX, + [3] = CPU1_GPIO_OUT3_IDX, + [4] = CPU1_GPIO_OUT4_IDX, + [5] = CPU1_GPIO_OUT5_IDX, + [6] = CPU1_GPIO_OUT6_IDX, + [7] = CPU1_GPIO_OUT7_IDX, + } + }, + }, +}; diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 8b43a903be1..49690cc7252 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### +config SOC_DEDICATED_GPIO_SUPPORTED + bool + default y + config SOC_UART_SUPPORTED bool default y @@ -291,6 +295,14 @@ config SOC_GPIO_OUT_RANGE_MAX int default 39 +config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER + bool + default y + +config SOC_GPIO_FLEX_GLITCH_FILTER_NUM + int + default 8 + config SOC_GPIO_SUPPORT_ETM bool default y diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index 95f9a1c9d1d..4ce1634620b 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -428,6 +428,23 @@ typedef enum { SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */ } soc_periph_sdm_clk_src_t; +//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Glitch Filter + */ +#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL} + +/** + * @brief Glitch filter clock source + */ + +typedef enum { + GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */ +} soc_periph_glitch_filter_clk_src_t; + //////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 429546053cd..bdbd92c1f94 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -33,7 +33,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ // #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12368 IDF-12370 // #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12395 big change!! -// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12401 +#define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_AHB_GDMA_SUPPORTED 1 @@ -201,8 +201,8 @@ #define SOC_GPIO_VALID_GPIO_MASK ((1ULL<