feat(clk): Add basic clock support for esp32h4

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -98,6 +98,8 @@ typedef enum {
     SOC_RTC_SLOW_CLK_SRC_RC32K = 2,        /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
     SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3,     /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
     SOC_RTC_SLOW_CLK_SRC_INVALID,          /*!< Invalid RTC_SLOW_CLK source */
+
+    SOC_RTC_SLOW_CLK_SRC_DEFAULT = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< RC_SLOW_CLK is the default clock source for RTC_SLOW_CLK */
 } soc_rtc_slow_clk_src_t;
 
 /**

components/soc/esp32h2/include/soc/soc.h

@@ -134,13 +134,9 @@
 //}}
 
 //Periheral Clock {{
-#define  APB_CLK_FREQ_ROM                            ( 32*1000000 )
-#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
-#define  CPU_CLK_FREQ_MHZ_BTLD                       (64)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  APB_CLK_FREQ                                ( 32*1000000 )
 #define  MODEM_REQUIRED_MIN_APB_CLK_FREQ             ( 32*1000000 )
 #define  REF_CLK_FREQ                                ( 1000000 )
-#define  XTAL_CLK_FREQ                               (32*1000000)
 //}}
 
 /* Overall memory map */