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Merge branch 'fix/psram-ecc-mspi-dma-align_v6.1' into 'release/v6.1'

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fix(mspi): handle PSRAM ECC DMA alignment across MSPI users (v6.1)

See merge request espressif/esp-idf!52363
This commit is contained in:
morris
2026-09-04 18:48:05 +08:00
parent 59512efe9c bd2d64bffb
commit 28a4aaa1db
59 changed files with 805 additions and 457 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/mbedtls/CMakeLists.txt
+2
View File
@@ -369,6 +369,8 @@ if(CONFIG_SOC_SHA_GDMA OR CONFIG_SOC_AES_GDMA)
endif()
if((SHA_PERIPHERAL_TYPE STREQUAL "core" AND CONFIG_SOC_SHA_SUPPORT_DMA) OR AES_PERIPHERAL_TYPE STREQUAL "dma")
target_link_libraries(tfpsacrypto PRIVATE idf::esp_hw_support)
target_link_libraries(builtin PRIVATE idf::esp_hw_support)
target_link_libraries(tfpsacrypto PRIVATE idf::esp_mm)
target_link_libraries(builtin PRIVATE idf::esp_mm)
if(CONFIG_SOC_SHA_GDMA OR CONFIG_SOC_AES_GDMA)
components/mbedtls/port/aes/dma/esp_aes_dma_core.c
+58 -42
View File
@@ -12,6 +12,7 @@
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_memory_utils.h"
#include "esp_private/esp_mspi_align.h"
#include "esp_private/periph_ctrl.h"
#include "soc/soc_caps.h"
#include "sdkconfig.h"
@@ -43,10 +44,6 @@
#include "aes/esp_aes_gcm.h"
#endif
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
#include "hal/efuse_hal.h"
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
/* Max size of each chunk to process when output buffer is in unaligned external ram
must be a multiple of block size
*/
@@ -249,22 +246,33 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
size_t input_alignment = 1;
size_t output_alignment = 1;
/* When AES-DMA operations are carried out using external memory with external memory encryption enabled,
we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned.
This is only applicable for ESP32-P4, as other targets use internal memory for DMA operations. */
#ifdef SOC_MEMSPI_ENCRYPTION_ALIGNMENT
/* When AES-DMA operations use external memory under MSPI strict alignment (FE or PSRAM ECC),
bounce buffers must be aligned to the MSPI requirement. On ESP32-P4, cache-line alignment
may also apply because DMA accesses cached external memory directly. */
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
if (efuse_hal_flash_encryption_enabled()) {
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
size_t input_mspi_align = esp_mspi_get_alignment(input);
size_t output_mspi_align = esp_mspi_get_alignment(output);
if (input_mspi_align > 1 || output_mspi_align > 1) {
size_t input_cache_line_size = get_cache_line_size(input);
size_t output_cache_line_size = get_cache_line_size(output);
input_alignment = MAX(input_cache_line_size, SOC_GDMA_EXT_MEM_ENC_ALIGNMENT);
output_alignment = MAX(output_cache_line_size, SOC_GDMA_EXT_MEM_ENC_ALIGNMENT);
input_alignment = MAX(input_cache_line_size, input_mspi_align);
output_alignment = MAX(output_cache_line_size, output_mspi_align);
input_heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(input) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
output_heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(output) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
}
}
#endif /* SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE */
#else
if (realloc_input && (esp_ptr_external_ram(input) || esp_ptr_in_drom(input))) {
input_alignment = esp_mspi_get_alignment(input);
}
if (realloc_output && (esp_ptr_external_ram(output) || esp_ptr_in_drom(output))) {
output_alignment = esp_mspi_get_alignment(output);
}
#endif
#endif /* SOC_MEMSPI_ENCRYPTION_ALIGNMENT */
if (realloc_input) {
input_buf = heap_caps_aligned_alloc(input_alignment, chunk_len, input_heap_caps);
@@ -280,7 +288,8 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
if (output_buf == NULL) {
mbedtls_platform_zeroize(output, len);
ESP_LOGE(TAG, "Failed to allocate memory");
return -1;
ret = -1;
goto cleanup;
}
} else {
output_buf = output;
@@ -358,9 +367,9 @@ static inline void dma_desc_append(crypto_dma_desc_t **head, crypto_dma_desc_t *
#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1))
#define AES_DMA_ALLOC_CAPS (MALLOC_CAP_DMA | MALLOC_CAP_8BIT)
static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size)
static inline void *aes_dma_calloc(size_t alignment, size_t num, size_t size, uint32_t caps, size_t *actual_size)
{
return heap_caps_aligned_calloc(DMA_DESC_MEM_ALIGN_SIZE, num, size, caps);
return heap_caps_aligned_calloc(alignment, num, size, caps);
}
static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_dma_desc_num, size_t buffer_cache_line_size)
@@ -429,6 +438,14 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
uint8_t *end_alignment_stream_buffer = NULL;
crypto_dma_desc_t *dma_descriptors = NULL;
size_t buffer_alignment = DMA_DESC_MEM_ALIGN_SIZE;
#ifdef SOC_MEMSPI_ENCRYPTION_ALIGNMENT
size_t mspi_alignment = esp_mspi_get_alignment(buffer);
buffer_alignment = MAX(buffer_alignment, mspi_alignment);
#endif
buffer_alignment = MAX(buffer_alignment, cache_line_size);
uint32_t alignment_buffer_caps = AES_DMA_ALLOC_CAPS |
(esp_ptr_external_ram(buffer) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_INTERNAL);
if (len == 0) {
goto ret;
@@ -459,7 +476,8 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
dma_descs_needed = (unaligned_start_bytes ? 1 : 0) + dma_desc_get_required_num(aligned_block_bytes, max_desc_size) + (unaligned_end_bytes ? 1 : 0);
/* Allocate memory for DMA descriptors of total size aligned up to a multiple of cache line size */
dma_descriptors = (crypto_dma_desc_t *) aes_dma_calloc(dma_descs_needed, sizeof(crypto_dma_desc_t), MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, NULL);
dma_descriptors = (crypto_dma_desc_t *) aes_dma_calloc(DMA_DESC_MEM_ALIGN_SIZE, dma_descs_needed,
sizeof(crypto_dma_desc_t), MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, NULL);
if (dma_descriptors == NULL) {
ESP_LOGE(TAG, "Failed to allocate memory for the array of DMA descriptors");
goto err;
@@ -468,7 +486,8 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
size_t populated_dma_descs = 0;
if (unaligned_start_bytes) {
start_alignment_stream_buffer = aes_dma_calloc(alignment_buffer_size, sizeof(uint8_t), AES_DMA_ALLOC_CAPS | (esp_ptr_external_ram(buffer) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_INTERNAL) , NULL);
start_alignment_stream_buffer = aes_dma_calloc(buffer_alignment, alignment_buffer_size,
sizeof(uint8_t), alignment_buffer_caps, NULL);
if (start_alignment_stream_buffer == NULL) {
ESP_LOGE(TAG, "Failed to allocate memory for start alignment buffer");
goto err;
@@ -490,7 +509,8 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
}
if (unaligned_end_bytes) {
end_alignment_stream_buffer = aes_dma_calloc(alignment_buffer_size, sizeof(uint8_t), AES_DMA_ALLOC_CAPS | (esp_ptr_external_ram(buffer) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_INTERNAL), NULL);
end_alignment_stream_buffer = aes_dma_calloc(buffer_alignment, alignment_buffer_size,
sizeof(uint8_t), alignment_buffer_caps, NULL);
if (end_alignment_stream_buffer == NULL) {
ESP_LOGE(TAG, "Failed to allocate memory for end alignment buffer");
goto err;
@@ -566,19 +586,17 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
}
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
if (efuse_hal_flash_encryption_enabled()) {
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
if (((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
input_needs_realloc = true;
}
#ifdef SOC_MEMSPI_ENCRYPTION_ALIGNMENT
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
if (!esp_mspi_buffer_alignment_satisfied(input, block_bytes)) {
input_needs_realloc = true;
}
if (((intptr_t)(output) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
output_needs_realloc = true;
}
if (!esp_mspi_buffer_alignment_satisfied(output, block_bytes)) {
output_needs_realloc = true;
}
}
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
#endif /* SOC_MEMSPI_ENCRYPTION_ALIGNMENT */
/* DMA cannot access memory in the iCache range, copy input to internal ram */
if (!s_check_dma_capable(input)) {
@@ -833,14 +851,14 @@ int esp_aes_process_dma_gcm(esp_aes_context *ctx, const unsigned char *input, un
out_desc_tail = &output_desc[output_dma_desc_num - 1];
len_desc = aes_dma_calloc(1, sizeof(crypto_dma_desc_t), AES_DMA_ALLOC_CAPS, NULL);
len_desc = aes_dma_calloc(DMA_DESC_MEM_ALIGN_SIZE, 1, sizeof(crypto_dma_desc_t), AES_DMA_ALLOC_CAPS, NULL);
if (len_desc == NULL) {
mbedtls_platform_zeroize(output, len);
ESP_LOGE(TAG, "Failed to allocate memory for len descriptor");
return -1;
}
uint32_t *len_buf = aes_dma_calloc(4, sizeof(uint32_t), AES_DMA_ALLOC_CAPS, NULL);
uint32_t *len_buf = aes_dma_calloc(DMA_DESC_MEM_ALIGN_SIZE, 4, sizeof(uint32_t), AES_DMA_ALLOC_CAPS, NULL);
if (len_buf == NULL) {
mbedtls_platform_zeroize(output, len);
ESP_LOGE(TAG, "Failed to allocate memory for len buffer");
@@ -1080,20 +1098,18 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
if (block_bytes > 0) {
/* Flush cache if input in external ram */
#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
if (efuse_hal_flash_encryption_enabled()) {
if (esp_ptr_external_ram(input) || esp_ptr_in_drom(input)) {
if (((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
input_needs_realloc = true;
}
}
if (esp_ptr_external_ram(output) || esp_ptr_in_drom(output)) {
if (((intptr_t)(output) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
output_needs_realloc = true;
}
#ifdef SOC_MEMSPI_ENCRYPTION_ALIGNMENT
if (esp_ptr_external_ram(input) || esp_ptr_in_drom(input)) {
if (!esp_mspi_buffer_alignment_satisfied(input, block_bytes)) {
input_needs_realloc = true;
}
}
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
if (esp_ptr_external_ram(output) || esp_ptr_in_drom(output)) {
if (!esp_mspi_buffer_alignment_satisfied(output, block_bytes)) {
output_needs_realloc = true;
}
}
#endif /* SOC_MEMSPI_ENCRYPTION_ALIGNMENT */
if (esp_ptr_external_ram(input)) {
if (esp_cache_msync((void *)input, len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED) != ESP_OK) {
components/mbedtls/port/sha/core/sha.c
+23 -24
View File
@@ -44,9 +44,9 @@
#include "esp_sha_dma_priv.h"
#include "sdkconfig.h"
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
#include "hal/efuse_hal.h"
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
#ifdef SOC_MEMSPI_ENCRYPTION_ALIGNMENT
#include "esp_private/esp_mspi_align.h"
#endif /* SOC_MEMSPI_ENCRYPTION_ALIGNMENT */
#if SOC_SHA_CRYPTO_DMA
#include "hal/crypto_dma_ll.h"
@@ -155,7 +155,7 @@ static DRAM_ATTR crypto_dma_desc_t s_dma_descr_buf;
static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
const void *buf, uint32_t buf_len, bool is_first_block);
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
#ifdef SOC_MEMSPI_ENCRYPTION_ALIGNMENT
static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *input, uint32_t ilen,
const void *buf, uint32_t buf_len, bool is_first_block,
bool realloc_input, bool realloc_buf)
@@ -171,7 +171,7 @@ static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *inpu
if (realloc_input) {
heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(input) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
input_copy = heap_caps_aligned_alloc(SOC_GDMA_EXT_MEM_ENC_ALIGNMENT, ilen, heap_caps);
input_copy = heap_caps_aligned_alloc(esp_mspi_get_alignment(input), ilen, heap_caps);
if (input_copy == NULL) {
ESP_LOGE(TAG, "Failed to allocate aligned SPIRAM memory");
return ret;
@@ -184,7 +184,7 @@ static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *inpu
if (realloc_buf) {
heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(buf) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
buf_copy = heap_caps_aligned_alloc(SOC_GDMA_EXT_MEM_ENC_ALIGNMENT, buf_len, heap_caps);
buf_copy = heap_caps_aligned_alloc(esp_mspi_get_alignment(buf), buf_len, heap_caps);
if (buf_copy == NULL) {
ESP_LOGE(TAG, "Failed to allocate aligned internal memory");
if (input_copy) {
@@ -213,7 +213,7 @@ static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *inpu
return ret;
}
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
#endif /* SOC_MEMSPI_ENCRYPTION_ALIGNMENT */
/* Performs SHA on multiple blocks at a time */
static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
@@ -232,28 +232,27 @@ static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, u
memset(&s_dma_descr_input, 0, sizeof(crypto_dma_desc_t));
memset(&s_dma_descr_buf, 0, sizeof(crypto_dma_desc_t));
/* When SHA-DMA operations are carried out using external memory with external memory encryption enabled,
we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned. */
#ifdef SOC_GDMA_EXT_MEM_ENC_ALIGNMENT
if (efuse_hal_flash_encryption_enabled()) {
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(buf) || esp_ptr_in_drom(input) || esp_ptr_in_drom(buf)) {
bool input_needs_realloc = false;
bool buf_needs_realloc = false;
/* When SHA-DMA operations are carried out using external memory with MSPI strict alignment enabled,
we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are aligned. */
#ifdef SOC_MEMSPI_ENCRYPTION_ALIGNMENT
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(buf) || esp_ptr_in_drom(input) || esp_ptr_in_drom(buf)) {
bool input_needs_realloc = false;
bool buf_needs_realloc = false;
if (ilen && ((intptr_t)(input) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
input_needs_realloc = true;
}
/* Skip when length is zero: buffer is unused and ptr may be NULL. */
if (ilen && !esp_mspi_buffer_alignment_satisfied(input, ilen)) {
input_needs_realloc = true;
}
if (buf_len && ((intptr_t)(buf) & (SOC_GDMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
buf_needs_realloc = true;
}
if (buf_len && !esp_mspi_buffer_alignment_satisfied(buf, buf_len)) {
buf_needs_realloc = true;
}
if (input_needs_realloc || buf_needs_realloc) {
return esp_sha_dma_process_ext(sha_type, input, ilen, buf, buf_len, is_first_block, input_needs_realloc, buf_needs_realloc);
}
if (input_needs_realloc || buf_needs_realloc) {
return esp_sha_dma_process_ext(sha_type, input, ilen, buf, buf_len, is_first_block, input_needs_realloc, buf_needs_realloc);
}
}
#endif /* SOC_GDMA_EXT_MEM_ENC_ALIGNMENT */
#endif /* SOC_MEMSPI_ENCRYPTION_ALIGNMENT */
/* DMA descriptor for Memory to DMA-SHA transfer */
if (ilen) {
components/mbedtls/test_apps/.build-test-rules.yml
+1
View File
@@ -5,6 +5,7 @@ components/mbedtls/test_apps/mbedtls_ut:
- if: CONFIG_NAME == "aes_no_hw" and SOC_AES_SUPPORTED != 1
- if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
- if: CONFIG_NAME == "psram_all_ext" and SOC_SPIRAM_SUPPORTED != 1
- if: CONFIG_NAME == "psram_ecc" and (SOC_SPIRAM_SUPPORTED != 1 or SOC_PSRAM_DMA_CAPABLE != 1 or SOC_AES_SUPPORT_DMA != 1 or IDF_TARGET == "esp32s2")
- if: CONFIG_NAME == "psram_all_ext_flash_enc" and SOC_SPIRAM_SUPPORTED != 1
- if: CONFIG_NAME == "psram_all_ext_flash_enc_f4r8" and IDF_TARGET != "esp32s3"
- if: CONFIG_NAME == "ecdsa_sign" and SOC_ECDSA_SUPPORTED != 1
components/mbedtls/test_apps/mbedtls_ut/include/crypto_performance.h
+1 -1
View File
@@ -35,7 +35,7 @@
#define IDF_PERFORMANCE_MIN_AES_GCM_UPDATE_THROUGHPUT_MBSEC 2.1
// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90.0
#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 88.0
// esp_sha() time to process 32KB of input data from RAM
#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 900
#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900
components/mbedtls/test_apps/mbedtls_ut/main/test_psa_aes.c
+99
View File
@@ -1846,6 +1846,105 @@ TEST_CASE("mbedtls AES internal mem alignment tests", "[aes]")
#ifdef CONFIG_SPIRAM_USE_MALLOC
#if CONFIG_SPIRAM_ECC_ENABLE && SOC_AES_SUPPORT_DMA
#define TEST_AES_PAYLOAD_LEN 53
struct aes_payload_sim_hdr {
uint8_t type;
uint8_t fc;
uint8_t seq;
uint8_t len;
uint8_t data[];
} __attribute__((packed));
static void aes_psram_ecc_cfb128_inplace_test(void)
{
const size_t pkt_len = sizeof(struct aes_payload_sim_hdr) + TEST_AES_PAYLOAD_LEN;
struct aes_payload_sim_hdr *pkt = heap_caps_aligned_alloc(16, pkt_len, PSRAM_DMA_CAPS);
uint8_t *backup = heap_caps_malloc(TEST_AES_PAYLOAD_LEN, INTERNAL_DMA_CAPS);
uint8_t key[16];
uint8_t iv[16];
psa_key_id_t key_id;
psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT;
psa_status_t status;
size_t output_len;
size_t total_len;
TEST_ASSERT_NOT_NULL(pkt);
TEST_ASSERT_NOT_NULL(backup);
TEST_ASSERT_TRUE(esp_ptr_external_ram(pkt));
TEST_ASSERT_EQUAL_UINT32(0, (uintptr_t)pkt & 0x0F);
TEST_ASSERT_EQUAL_UINT32(sizeof(struct aes_payload_sim_hdr) & 0x0F, (uintptr_t)pkt->data & 0x0F);
pkt->type = 0x13;
pkt->fc = 0x04;
pkt->seq = 1;
pkt->len = TEST_AES_PAYLOAD_LEN;
for (size_t i = 0; i < TEST_AES_PAYLOAD_LEN; i++) {
pkt->data[i] = 0x3C + (uint8_t)(i & 0x0F);
}
memcpy(backup, pkt->data, TEST_AES_PAYLOAD_LEN);
memset(key, 0x5A, sizeof(key));
memset(iv, 0xA5, sizeof(iv));
iv[0] = 3;
status = psa_crypto_init();
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT);
psa_set_key_algorithm(&attributes, PSA_ALG_CFB);
psa_set_key_type(&attributes, PSA_KEY_TYPE_AES);
psa_set_key_bits(&attributes, 128);
status = psa_import_key(&attributes, key, sizeof(key), &key_id);
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
psa_cipher_operation_t operation = PSA_CIPHER_OPERATION_INIT;
status = psa_cipher_encrypt_setup(&operation, key_id, PSA_ALG_CFB);
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
status = psa_cipher_set_iv(&operation, iv, sizeof(iv));
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
total_len = 0;
status = psa_cipher_update(&operation, pkt->data, TEST_AES_PAYLOAD_LEN, pkt->data, TEST_AES_PAYLOAD_LEN, &output_len);
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
total_len += output_len;
status = psa_cipher_finish(&operation, pkt->data + output_len, TEST_AES_PAYLOAD_LEN - output_len, &output_len);
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
total_len += output_len;
TEST_ASSERT_EQUAL(TEST_AES_PAYLOAD_LEN, total_len);
memset(iv, 0xA5, sizeof(iv));
iv[0] = 3;
psa_cipher_abort(&operation);
operation = (psa_cipher_operation_t)PSA_CIPHER_OPERATION_INIT;
status = psa_cipher_decrypt_setup(&operation, key_id, PSA_ALG_CFB);
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
status = psa_cipher_set_iv(&operation, iv, sizeof(iv));
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
total_len = 0;
status = psa_cipher_update(&operation, pkt->data, TEST_AES_PAYLOAD_LEN, pkt->data, TEST_AES_PAYLOAD_LEN, &output_len);
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
total_len += output_len;
status = psa_cipher_finish(&operation, pkt->data + output_len, TEST_AES_PAYLOAD_LEN - output_len, &output_len);
TEST_ASSERT_EQUAL(PSA_SUCCESS, status);
total_len += output_len;
TEST_ASSERT_EQUAL(TEST_AES_PAYLOAD_LEN, total_len);
TEST_ASSERT_EQUAL_MEMORY(backup, pkt->data, TEST_AES_PAYLOAD_LEN);
psa_cipher_abort(&operation);
psa_destroy_key(key_id);
free(backup);
free(pkt);
}
TEST_CASE("mbedtls AES PSRAM ECC CFB128 in-place test", "[aes][psram_ecc_dma]")
{
aes_psram_ecc_cfb128_inplace_test();
}
#endif // CONFIG_SPIRAM_ECC_ENABLE && SOC_AES_SUPPORT_DMA
void aes_psram_one_buf_ctr_test(void)
{
psa_key_id_t key_id;
components/mbedtls/test_apps/mbedtls_ut/pytest_mbedtls_ut.py
+22
View File
@@ -5,6 +5,15 @@ from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
# esp32s2 has PSRAM DMA and AES DMA, but no PSRAM ECC Kconfig option.
PSRAM_ECC_DMA_TARGETS = [
target
for target in soc_filtered_targets(
'SOC_SPIRAM_SUPPORTED == 1 and SOC_PSRAM_DMA_CAPABLE == 1 and SOC_AES_SUPPORT_DMA == 1'
)
if target != 'esp32s2'
]
@pytest.mark.generic
@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='can not pass') # TODO: IDF-15675
@@ -53,6 +62,19 @@ def test_mbedtls_psram(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=180)
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
'psram_ecc',
],
indirect=True,
)
@idf_parametrize('target', PSRAM_ECC_DMA_TARGETS, indirect=['target'])
def test_mbedtls_psram_ecc(dut: Dut) -> None:
dut.run_all_single_board_cases(group='aes', timeout=180)
@pytest.mark.flash_encryption_psram
@pytest.mark.parametrize(
'config',
components/mbedtls/test_apps/mbedtls_ut/sdkconfig.ci.psram_ecc
+5
View File
@@ -0,0 +1,5 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_ECC_ENABLE=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800