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feat(parlio_tx): supported parlio tx on p4

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This commit is contained in:
laokaiyao
2023-09-25 10:42:30 +08:00
parent d42306c317
commit 28a45e20b8
17 changed files with 1083 additions and 71 deletions
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components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+5 -1
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@@ -35,6 +35,10 @@ config SOC_ETM_SUPPORTED
bool
default y
config SOC_PARLIO_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -651,7 +655,7 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
int
default 16
config SOC_PARLIO_TX_RX_SHARE_INTERRUPT
config SOC_PARLIO_TX_SIZE_BY_DMA
bool
default y
components/soc/esp32p4/include/soc/clk_tree_defs.h
+20
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@@ -448,6 +448,26 @@ typedef enum {
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PARLIO
*/
#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_RC_FAST, PARLIO_CLK_SRC_EXTERNAL}
/**
* @brief PARLIO clock source
*/
typedef enum {
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PARLIO_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
#if SOC_CLK_TREE_SUPPORTED
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_parlio_clk_src_t;
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/include/soc/parl_io_struct.h
+1
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@@ -498,6 +498,7 @@ typedef struct parl_io_dev_t {
volatile parl_io_version_reg_t version;
} parl_io_dev_t;
extern parl_io_dev_t PARL_IO;
#ifndef __cplusplus
_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
components/soc/esp32p4/include/soc/soc_caps.h
+2 -2
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@@ -37,7 +37,7 @@
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 //TODO: IDF-7470
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 //TODO: IDF-7471, TODO: IDF-7472
#define SOC_PARLIO_SUPPORTED 1 //TODO: IDF-7471
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
// disable usb serial jtag for esp32p4, current image does not support
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: IDF-7496
@@ -317,7 +317,7 @@
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */
#define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */
/*--------------------------- MPI CAPS ---------------------------------------*/
#define SOC_MPI_MEM_BLOCKS_NUM (4)
components/soc/esp32p4/parlio_periph.c
+55 -1
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@@ -8,5 +8,59 @@
#include "soc/gpio_sig_map.h"
const parlio_signal_conn_t parlio_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_PARLIO_MODULE,
.tx_irq_id = ETS_HP_PARLIO_TX_INTR_SOURCE,
.rx_irq_id = ETS_HP_PARLIO_RX_INTR_SOURCE,
.tx_units = {
[0] = {
.data_sigs = {
PARLIO_TX_DATA0_PAD_OUT_IDX,
PARLIO_TX_DATA1_PAD_OUT_IDX,
PARLIO_TX_DATA2_PAD_OUT_IDX,
PARLIO_TX_DATA3_PAD_OUT_IDX,
PARLIO_TX_DATA4_PAD_OUT_IDX,
PARLIO_TX_DATA5_PAD_OUT_IDX,
PARLIO_TX_DATA6_PAD_OUT_IDX,
PARLIO_TX_DATA7_PAD_OUT_IDX,
PARLIO_TX_DATA8_PAD_OUT_IDX,
PARLIO_TX_DATA9_PAD_OUT_IDX,
PARLIO_TX_DATA10_PAD_OUT_IDX,
PARLIO_TX_DATA11_PAD_OUT_IDX,
PARLIO_TX_DATA12_PAD_OUT_IDX,
PARLIO_TX_DATA13_PAD_OUT_IDX,
PARLIO_TX_DATA14_PAD_OUT_IDX,
PARLIO_TX_DATA15_PAD_OUT_IDX,
},
.clk_out_sig = PARLIO_TX_CLK_PAD_OUT_IDX,
.clk_in_sig = PARLIO_TX_CLK_PAD_IN_IDX,
}
},
.rx_units = {
[0] = {
.data_sigs = {
PARLIO_RX_DATA0_PAD_IN_IDX,
PARLIO_RX_DATA1_PAD_IN_IDX,
PARLIO_RX_DATA2_PAD_IN_IDX,
PARLIO_RX_DATA3_PAD_IN_IDX,
PARLIO_RX_DATA4_PAD_IN_IDX,
PARLIO_RX_DATA5_PAD_IN_IDX,
PARLIO_RX_DATA6_PAD_IN_IDX,
PARLIO_RX_DATA7_PAD_IN_IDX,
PARLIO_RX_DATA8_PAD_IN_IDX,
PARLIO_RX_DATA9_PAD_IN_IDX,
PARLIO_RX_DATA10_PAD_IN_IDX,
PARLIO_RX_DATA11_PAD_IN_IDX,
PARLIO_RX_DATA12_PAD_IN_IDX,
PARLIO_RX_DATA13_PAD_IN_IDX,
PARLIO_RX_DATA14_PAD_IN_IDX,
PARLIO_RX_DATA15_PAD_IN_IDX,
},
.clk_out_sig = PARLIO_RX_CLK_PAD_OUT_IDX,
.clk_in_sig = PARLIO_RX_CLK_PAD_IN_IDX,
}
}
},
},
};