Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-01 18:50:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'fix/handle_shared_intr_v6.0' into 'release/v6.0'

Browse Source 
Fix/handle shared intr (v6.0)

See merge request espressif/esp-idf!43504
This commit is contained in:
morris
2025-11-27 11:43:51 +08:00
parent 2e470da924 443c5b0832
commit 28999c8162
46 changed files with 407 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/esp32/include/hal/ledc_ll.h
+14 -1
View File
@@ -26,6 +26,8 @@ extern "C" {
#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V)
#define LEDC_LL_FRACTIONAL_BITS (8)
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
/// Get the mask of the fade end interrupt status register.
#define LEDC_LL_FADE_END_INTR_MASK (0xffffUL << LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S)
#define LEDC_LL_GLOBAL_CLOCKS { \
LEDC_SLOW_CLK_APB, \
@@ -556,7 +558,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
*
* @param hw Beginning address of the peripheral registers
* @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
* @param channel_num LEDC channel index (0-7), select from ledc_channel_t
* @param intr_status The fade end interrupt status
*
* @return None
@@ -568,6 +569,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
*intr_status = (value >> int_en_base) & 0xff;
}
/**
* @brief Get the address of the fade end interrupt status register.
*
* @param hw Beginning address of the peripheral registers
* @return Pointer to the fade end interrupt status register.
*/
static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
{
return &hw->int_st.val;
}
/**
* @brief Clear fade end interrupt status
*
components/hal/esp32/include/hal/sdio_slave_ll.h
+13
View File
@@ -37,6 +37,8 @@ extern "C" {
#define sdio_slave_ll_get_host(ID) (&HOST)
/// Get address of the only HINF registers for ESP32
#define sdio_slave_ll_get_hinf(ID) (&HINF)
/// Get the mask of the interrupt status.
#define sdio_slave_ll_intr_status_mask (0xff | SLC_SLC0_RX_DONE_INT_ST | SLC_SLC0_RX_EOF_INT_ST | SLC_SLC0_TX_DONE_INT_ST)
/*
* SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
@@ -550,6 +552,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l
slc->slc0_int_clr.val = slv_int;
}
/**
* Get the address of the interrupt status register.
*
* @param slc Address of the SLC registers
* @return Address of the interrupt status register
*/
static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc)
{
return &slc->slc0_int_st.val;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32/include/hal/uart_ll.h
+5 -1
View File
@@ -37,7 +37,6 @@ extern "C" {
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1<<0),
@@ -300,6 +299,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
return hw->int_st.val;
}
FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
{
return &hw->int_st.val;
}
/**
* @brief Clear the UART interrupt status based on the given mask.
*