From f7c46393b23cd8e2448264573830418716365811 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 24 Jul 2026 15:02:48 +0800 Subject: [PATCH 1/2] refactor(lcd): rename delay_ticks to delay_mode to match register semantics The LCD delay registers configure a delay mode (0=no delay, 1=delay on rising edge, 2=delay on falling edge), not a tick count. Rename the LL layer functions and parameters to reflect this, and add lcd_ll_set_data_delay_mode for esp32s31 and esp32p4. --- .../esp_hal_cam/esp32p4/include/hal/cam_ll.h | 24 ---------- .../esp_hal_cam/esp32s3/include/hal/cam_ll.h | 24 ---------- .../esp_hal_cam/esp32s31/include/hal/cam_ll.h | 25 ---------- .../esp_hal_lcd/esp32p4/include/hal/lcd_ll.h | 44 ++++++++++++----- .../esp_hal_lcd/esp32s3/include/hal/lcd_ll.h | 32 ++++++------- .../esp_hal_lcd/esp32s31/include/hal/lcd_ll.h | 47 ++++++++++++++----- 6 files changed, 82 insertions(+), 114 deletions(-) diff --git a/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h b/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h index 7a42801cd76..4a6aa116352 100644 --- a/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h +++ b/components/esp_hal_cam/esp32p4/include/hal/cam_ll.h @@ -128,30 +128,6 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src) cam_ll_select_clk_src(__VA_ARGS__); \ } while(0) -/** - * @brief Get the CAM source clock type - * - * @param dev CAM register base address - * @param src The pointer to accept the CAM source clock type - */ -static inline void cam_ll_get_clk_src(lcd_cam_dev_t *dev, cam_clock_source_t *src) -{ - switch (HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel) { - case 0: - *src = CAM_CLK_SRC_XTAL; - break; - case 1: - *src = CAM_CLK_SRC_PLL160M; - break; - case 2: - *src = CAM_CLK_SRC_APLL; - break; - default: - HAL_ASSERT(false); - break; - } -} - /** * @brief Set clock coefficient of CAM peripheral * diff --git a/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h b/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h index 2b58c45f76f..16665fde5d4 100644 --- a/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h +++ b/components/esp_hal_cam/esp32s3/include/hal/cam_ll.h @@ -99,30 +99,6 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src) } } -/** - * @brief Get the CAM source clock type - * - * @param dev CAM register base address - * @param src The pointer to accept the CAM source clock type - */ -static inline void cam_ll_get_clk_src(lcd_cam_dev_t *dev, cam_clock_source_t *src) -{ - switch (LCD_CAM.cam_ctrl.cam_clk_sel) { - case 1: - *src = CAM_CLK_SRC_XTAL; - break; - case 2: - *src = CAM_CLK_SRC_PLL240M; - break; - case 3: - *src = CAM_CLK_SRC_PLL160M; - break; - default: - HAL_ASSERT(false); - break; - } -} - /** * @brief Set clock coefficient of CAM peripheral * diff --git a/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h b/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h index 2bb647532f4..6043b2d4850 100644 --- a/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h +++ b/components/esp_hal_cam/esp32s31/include/hal/cam_ll.h @@ -104,31 +104,6 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src) } } -/** - * @brief Get the CAM source clock type - * - * @param dev CAM register base address - * @param src The pointer to accept the CAM source clock type - */ -static inline void cam_ll_get_clk_src(lcd_cam_dev_t *dev, cam_clock_source_t *src) -{ - (void)dev; - switch (HP_SYS_CLKRST.lcdcam_cam_ctrl0.reg_cam_clk_src_sel) { - case 0: - *src = CAM_CLK_SRC_XTAL; - break; - case 1: - *src = CAM_CLK_SRC_PLL160M; - break; - case 2: - *src = CAM_CLK_SRC_APLL; - break; - default: - HAL_ASSERT(false); - break; - } -} - /** * @brief Set clock coefficient of CAM peripheral * diff --git a/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h b/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h index 443e61be6b8..2984647ff9e 100644 --- a/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h +++ b/components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h @@ -662,14 +662,14 @@ static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool } /** - * @brief Set cycle of delay for DC line + * @brief Set delay mode for DC line * * @param dev LCD register base address - * @param delay Ticks of delay + * @param mode Delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge */ -static inline void lcd_ll_set_dc_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay) +static inline void lcd_ll_set_dc_delay_mode(lcd_cam_dev_t *dev, uint32_t mode) { - dev->lcd_dly_mode_cfg1.lcd_cd_mode = delay; + dev->lcd_dly_mode_cfg1.lcd_cd_mode = mode; } /** @@ -789,18 +789,38 @@ static inline void lcd_ll_set_idle_level(lcd_cam_dev_t *dev, bool hsync_idle_lev } /** - * @brief Set extra delay for HSYNC, VSYNC, and DE signals + * @brief Set delay mode for HSYNC, VSYNC, and DE signals * * @param dev LCD register base address - * @param hsync_delay HSYNC delay - * @param vsync_delay VSYNC delay - * @param de_delay DE delay + * @param hsync_mode HSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + * @param vsync_mode VSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + * @param de_mode DE delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge */ -static inline void lcd_ll_set_delay_ticks(lcd_cam_dev_t *dev, uint32_t hsync_delay, uint32_t vsync_delay, uint32_t de_delay) +static inline void lcd_ll_set_delay_mode(lcd_cam_dev_t *dev, uint32_t hsync_mode, uint32_t vsync_mode, uint32_t de_mode) { - dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_delay; - dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_delay; - dev->lcd_dly_mode_cfg1.lcd_de_mode = de_delay; + dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_mode; + dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_mode; + dev->lcd_dly_mode_cfg1.lcd_de_mode = de_mode; +} + +/** + * @brief Set delay mode for all data lines + * + * @param dev LCD register base address + * @param mode Data line delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + */ +static inline void lcd_ll_set_data_delay_mode(lcd_cam_dev_t *dev, uint32_t mode) +{ + uint32_t reg_val = 0; + for (int i = 0; i < 16; i++) { + reg_val |= (mode & 0x03) << (2 * i); + } + dev->lcd_dly_mode_cfg2.val = reg_val; + reg_val = 0; + for (int i = 0; i < 8; i++) { + reg_val |= (mode & 0x03) << (2 * i); + } + dev->lcd_dly_mode_cfg1.val = (dev->lcd_dly_mode_cfg1.val & 0xFFFF0000) | reg_val; } /** diff --git a/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h b/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h index 6164ddf39c7..001868f2484 100644 --- a/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h +++ b/components/esp_hal_lcd/esp32s3/include/hal/lcd_ll.h @@ -617,14 +617,14 @@ static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool } /** - * @brief Set cycle of delay for DC line + * @brief Set delay mode for DC line * * @param dev LCD register base address - * @param delay Ticks of delay + * @param mode Delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge */ -static inline void lcd_ll_set_dc_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay) +static inline void lcd_ll_set_dc_delay_mode(lcd_cam_dev_t *dev, uint32_t mode) { - dev->lcd_dly_mode.lcd_cd_mode = delay; + dev->lcd_dly_mode.lcd_cd_mode = mode; } /** @@ -741,31 +741,31 @@ static inline void lcd_ll_set_idle_level(lcd_cam_dev_t *dev, bool hsync_idle_lev } /** - * @brief Set extra delay for HSYNC, VSYNC, and DE signals + * @brief Set delay mode for HSYNC, VSYNC, and DE signals * * @param dev LCD register base address - * @param hsync_delay HSYNC delay - * @param vsync_delay VSYNC delay - * @param de_delay DE delay + * @param hsync_mode HSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + * @param vsync_mode VSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + * @param de_mode DE delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge */ -static inline void lcd_ll_set_delay_ticks(lcd_cam_dev_t *dev, uint32_t hsync_delay, uint32_t vsync_delay, uint32_t de_delay) +static inline void lcd_ll_set_delay_mode(lcd_cam_dev_t *dev, uint32_t hsync_mode, uint32_t vsync_mode, uint32_t de_mode) { - dev->lcd_dly_mode.lcd_hsync_mode = hsync_delay; - dev->lcd_dly_mode.lcd_vsync_mode = vsync_delay; - dev->lcd_dly_mode.lcd_de_mode = de_delay; + dev->lcd_dly_mode.lcd_hsync_mode = hsync_mode; + dev->lcd_dly_mode.lcd_vsync_mode = vsync_mode; + dev->lcd_dly_mode.lcd_de_mode = de_mode; } /** - * @brief Set extra delay for data lines + * @brief Set delay mode for all data lines * * @param dev LCD register base address - * @param delay Data line delay + * @param mode Data line delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge */ -static inline void lcd_ll_set_data_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay) +static inline void lcd_ll_set_data_delay_mode(lcd_cam_dev_t *dev, uint32_t mode) { uint32_t reg_val = 0; for (int i = 0; i < 16; i++) { - reg_val |= (delay & 0x03) << (2 * i); + reg_val |= (mode & 0x03) << (2 * i); } dev->lcd_data_dout_mode.val = reg_val; } diff --git a/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h b/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h index 7fc969ce91c..ea2b43500ba 100644 --- a/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h +++ b/components/esp_hal_lcd/esp32s31/include/hal/lcd_ll.h @@ -214,7 +214,8 @@ static inline void lcd_ll_mem_set_low_power_mode(lcd_cam_dev_t *dev, lcd_ll_mem_ /** * @brief Enable the transfer buffer(memory block) for LCD module * - * @note Only for RGB mode + * @note Only for RGB mode, and can't work with YUV420 color convert mode. + * * @param dev Peripheral instance address * @param en True to enable, False to disable */ @@ -652,14 +653,14 @@ static inline void lcd_ll_set_dc_level(lcd_cam_dev_t *dev, bool idle_phase, bool } /** - * @brief Set cycle of delay for DC line + * @brief Set delay mode for DC line * * @param dev LCD register base address - * @param delay Ticks of delay + * @param mode Delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge */ -static inline void lcd_ll_set_dc_delay_ticks(lcd_cam_dev_t *dev, uint32_t delay) +static inline void lcd_ll_set_dc_delay_mode(lcd_cam_dev_t *dev, uint32_t mode) { - dev->lcd_dly_mode_cfg1.lcd_cd_mode = delay; + dev->lcd_dly_mode_cfg1.lcd_cd_mode = mode; } /** @@ -779,18 +780,38 @@ static inline void lcd_ll_set_idle_level(lcd_cam_dev_t *dev, bool hsync_idle_lev } /** - * @brief Set extra delay for HSYNC, VSYNC, and DE signals + * @brief Set delay mode for HSYNC, VSYNC, and DE signals * * @param dev LCD register base address - * @param hsync_delay HSYNC delay - * @param vsync_delay VSYNC delay - * @param de_delay DE delay + * @param hsync_mode HSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + * @param vsync_mode VSYNC delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + * @param de_mode DE delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge */ -static inline void lcd_ll_set_delay_ticks(lcd_cam_dev_t *dev, uint32_t hsync_delay, uint32_t vsync_delay, uint32_t de_delay) +static inline void lcd_ll_set_delay_mode(lcd_cam_dev_t *dev, uint32_t hsync_mode, uint32_t vsync_mode, uint32_t de_mode) { - dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_delay; - dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_delay; - dev->lcd_dly_mode_cfg1.lcd_de_mode = de_delay; + dev->lcd_dly_mode_cfg1.lcd_hsync_mode = hsync_mode; + dev->lcd_dly_mode_cfg1.lcd_vsync_mode = vsync_mode; + dev->lcd_dly_mode_cfg1.lcd_de_mode = de_mode; +} + +/** + * @brief Set delay mode for all data lines + * + * @param dev LCD register base address + * @param mode Data line delay mode, 0: no delay, 1: delay on LCD_CLK rising edge, 2: delay on LCD_CLK falling edge + */ +static inline void lcd_ll_set_data_delay_mode(lcd_cam_dev_t *dev, uint32_t mode) +{ + uint32_t reg_val = 0; + for (int i = 0; i < 16; i++) { + reg_val |= (mode & 0x03) << (2 * i); + } + dev->lcd_dly_mode_cfg2.val = reg_val; + reg_val = 0; + for (int i = 0; i < 8; i++) { + reg_val |= (mode & 0x03) << (2 * i); + } + dev->lcd_dly_mode_cfg1.val = (dev->lcd_dly_mode_cfg1.val & 0xFFFF0000) | reg_val; } /** From 2a9d1ee20e5d0a745b9d0a894bd90b7e590dbfb2 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 24 Jul 2026 15:55:34 +0800 Subject: [PATCH 2/2] refactor(uhci): rename set_eof_mode to enable_eof_modes with bool en param MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename uhci_ll_rx_set_eof_mode → uhci_ll_rx_enable_eof_modes and its parameter eof_mode → eof_modes to reflect that multiple EOF modes can be enabled simultaneously via bitmask. Add bool en parameter so callers can enable or disable without an outer if-check. --- .../transport/driver/uart/hci_driver_uart_dma.c | 4 ++-- .../transport/driver/uart/hci_driver_uart_dma.c | 4 ++-- components/esp_driver_uart/src/uhci.c | 11 +++-------- .../esp_hal_uart/esp32c3/include/hal/uhci_ll.h | 14 +++++++------- .../esp_hal_uart/esp32c5/include/hal/uhci_ll.h | 14 +++++++------- .../esp_hal_uart/esp32c6/include/hal/uhci_ll.h | 14 +++++++------- .../esp_hal_uart/esp32h2/include/hal/uhci_ll.h | 14 +++++++------- .../esp_hal_uart/esp32h21/include/hal/uhci_ll.h | 14 +++++++------- .../esp_hal_uart/esp32h4/include/hal/uhci_ll.h | 16 ++++++++-------- .../esp_hal_uart/esp32p4/include/hal/uhci_ll.h | 14 +++++++------- .../esp_hal_uart/esp32s3/include/hal/uhci_ll.h | 14 +++++++------- .../esp_hal_uart/esp32s31/include/hal/uhci_ll.h | 16 ++++++++-------- 12 files changed, 72 insertions(+), 77 deletions(-) diff --git a/components/bt/porting/transport/driver/uart/hci_driver_uart_dma.c b/components/bt/porting/transport/driver/uart/hci_driver_uart_dma.c index 275961e9584..a50ddc57d5a 100644 --- a/components/bt/porting/transport/driver/uart/hci_driver_uart_dma.c +++ b/components/bt/porting/transport/driver/uart/hci_driver_uart_dma.c @@ -461,8 +461,8 @@ static void hci_driver_uart_dma_install(void) gdma_register_tx_event_callbacks(s_tx_channel, &tx_cbs, NULL); // configure UHCI uhci_ll_init((uhci_dev_t *)s_uhci_hw); - // uhci_ll_rx_set_eof_mode((uhci_dev_t *)s_uhci_hw, UHCI_RX_LEN_EOF); - uhci_ll_rx_set_eof_mode((uhci_dev_t *)s_uhci_hw, UHCI_RX_IDLE_EOF); + // uhci_ll_rx_enable_eof_modes((uhci_dev_t *)s_uhci_hw, UHCI_RX_LEN_EOF, true); + uhci_ll_rx_enable_eof_modes((uhci_dev_t *)s_uhci_hw, UHCI_RX_IDLE_EOF, true); // disable software flow control s_uhci_hw->escape_conf.val = 0; uhci_ll_attach_uart_port((uhci_dev_t *)s_uhci_hw, s_hci_driver_uart_dma_env.hci_uart_params->hci_uart_port); diff --git a/components/bt/porting_btdm/transport/driver/uart/hci_driver_uart_dma.c b/components/bt/porting_btdm/transport/driver/uart/hci_driver_uart_dma.c index c158ae7a709..ae2e8bef771 100644 --- a/components/bt/porting_btdm/transport/driver/uart/hci_driver_uart_dma.c +++ b/components/bt/porting_btdm/transport/driver/uart/hci_driver_uart_dma.c @@ -485,8 +485,8 @@ static void hci_driver_uart_dma_install(void) // configure UHCI uhci_ll_init((uhci_dev_t *)s_uhci_hw); - // uhci_ll_set_eof_mode((uhci_dev_t *)s_uhci_hw, UHCI_RX_LEN_EOF); - uhci_ll_set_eof_mode((uhci_dev_t *)s_uhci_hw, UHCI_RX_IDLE_EOF); + // uhci_ll_rx_enable_eof_modes((uhci_dev_t *)s_uhci_hw, UHCI_RX_LEN_EOF, true); + uhci_ll_rx_enable_eof_modes((uhci_dev_t *)s_uhci_hw, UHCI_RX_IDLE_EOF, true); // disable software flow control s_uhci_hw->escape_conf.val = 0; uhci_ll_attach_uart_port((uhci_dev_t *)s_uhci_hw, s_hci_driver_uart_dma_env.hci_uart_params->hci_uart_port); diff --git a/components/esp_driver_uart/src/uhci.c b/components/esp_driver_uart/src/uhci.c index 63e7ac4db1b..3ff2957f8e4 100644 --- a/components/esp_driver_uart/src/uhci.c +++ b/components/esp_driver_uart/src/uhci.c @@ -6,7 +6,6 @@ #include #include -#include "esp_intr_alloc.h" #if CONFIG_UHCI_ENABLE_DEBUG_LOG // The local log level must be defined before including esp_log.h // Set the maximum log level for this source file @@ -601,16 +600,12 @@ esp_err_t uhci_new_controller(const uhci_controller_config_t *config, uhci_contr }; uhci_ll_set_seper_chr(uhci_ctrl->hal.dev, &seper_chr); - if (config->rx_eof_flags.idle_eof) { - uhci_ll_rx_set_eof_mode(uhci_ctrl->hal.dev, UHCI_RX_IDLE_EOF); - } + uhci_ll_rx_enable_eof_modes(uhci_ctrl->hal.dev, UHCI_RX_IDLE_EOF, config->rx_eof_flags.idle_eof); + uhci_ll_rx_enable_eof_modes(uhci_ctrl->hal.dev, UHCI_RX_LEN_EOF, config->rx_eof_flags.length_eof); + uhci_ll_rx_enable_eof_modes(uhci_ctrl->hal.dev, UHCI_RX_BREAK_CHR_EOF, config->rx_eof_flags.rx_brk_eof); if (config->rx_eof_flags.length_eof) { - uhci_ll_rx_set_eof_mode(uhci_ctrl->hal.dev, UHCI_RX_LEN_EOF); uhci_ll_rx_set_packet_threshold(uhci_ctrl->hal.dev, config->max_packet_receive); } - if (config->rx_eof_flags.rx_brk_eof) { - uhci_ll_rx_set_eof_mode(uhci_ctrl->hal.dev, UHCI_RX_BREAK_CHR_EOF); - } esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &uhci_ctrl->ext_mem_cache_line_size); esp_cache_get_alignment(MALLOC_CAP_INTERNAL, &uhci_ctrl->int_mem_cache_line_size); diff --git a/components/esp_hal_uart/esp32c3/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32c3/include/hal/uhci_ll.h index 591befc749b..b4f6df32f00 100644 --- a/components/esp_hal_uart/esp32c3/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32c3/include/hal/uhci_ll.h @@ -154,16 +154,16 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) return hw->int_st.val; } -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32c5/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32c5/include/hal/uhci_ll.h index dbb5ea75699..53ad8d7244f 100644 --- a/components/esp_hal_uart/esp32c5/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32c5/include/hal/uhci_ll.h @@ -138,16 +138,16 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) return hw->int_st.val; } -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32c6/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32c6/include/hal/uhci_ll.h index f2f3fe57bce..10a2e45d712 100644 --- a/components/esp_hal_uart/esp32c6/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32c6/include/hal/uhci_ll.h @@ -140,16 +140,16 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) return hw->int_st.val; } -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32h2/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32h2/include/hal/uhci_ll.h index 93bff9eb2b3..7614f70713f 100644 --- a/components/esp_hal_uart/esp32h2/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32h2/include/hal/uhci_ll.h @@ -136,16 +136,16 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) return hw->int_st.val; } -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32h21/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32h21/include/hal/uhci_ll.h index 23d68888b92..9d05ed639b2 100644 --- a/components/esp_hal_uart/esp32h21/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32h21/include/hal/uhci_ll.h @@ -136,16 +136,16 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) return hw->int_st.val; } -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32h4/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32h4/include/hal/uhci_ll.h index 63196606926..b2b118b6a44 100644 --- a/components/esp_hal_uart/esp32h4/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32h4/include/hal/uhci_ll.h @@ -186,21 +186,21 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) * @brief Set the EOF mode for payload receive * * @param hw Pointer to the UHCI device - * @param eof_mode The EOF mode to set. The following modes are supported: + * @param eof_modes The EOF mode to set. The following modes are supported: * - UHCI_RX_BREAK_CHR_EOF: UHCI will end payload receive process when NULL frame is received by UART. * - UHCI_RX_IDLE_EOF: UHCI will end payload receive process when UART has been in idle state. * - UHCI_RX_LEN_EOF: UHCI will end payload receive process when the receiving byte count has reached the specific value. */ -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32p4/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32p4/include/hal/uhci_ll.h index d296e71b8d6..c94209d0d2a 100644 --- a/components/esp_hal_uart/esp32p4/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32p4/include/hal/uhci_ll.h @@ -102,16 +102,16 @@ static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper } } -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32s3/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32s3/include/hal/uhci_ll.h index a200c491610..020164d8e49 100644 --- a/components/esp_hal_uart/esp32s3/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32s3/include/hal/uhci_ll.h @@ -155,16 +155,16 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) return hw->int_st.val; } -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } } diff --git a/components/esp_hal_uart/esp32s31/include/hal/uhci_ll.h b/components/esp_hal_uart/esp32s31/include/hal/uhci_ll.h index f0ed5b60fb3..5b171bebb66 100644 --- a/components/esp_hal_uart/esp32s31/include/hal/uhci_ll.h +++ b/components/esp_hal_uart/esp32s31/include/hal/uhci_ll.h @@ -187,21 +187,21 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) * @brief Set the EOF mode for payload receive * * @param hw Pointer to the UHCI device - * @param eof_mode The EOF mode to set. The following modes are supported: + * @param eof_modes The EOF mode to set. The following modes are supported: * - UHCI_RX_BREAK_CHR_EOF: UHCI will end payload receive process when NULL frame is received by UART. * - UHCI_RX_IDLE_EOF: UHCI will end payload receive process when UART has been in idle state. * - UHCI_RX_LEN_EOF: UHCI will end payload receive process when the receiving byte count has reached the specific value. */ -static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) +static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en) { - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; + if (eof_modes & UHCI_RX_BREAK_CHR_EOF) { + hw->conf0.uart_rx_brk_eof_en = en; } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; + if (eof_modes & UHCI_RX_IDLE_EOF) { + hw->conf0.uart_idle_eof_en = en; } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; + if (eof_modes & UHCI_RX_LEN_EOF) { + hw->conf0.len_eof_en = en; } }