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fix(esp_eth): correct PHYCFGR sanity check mask and bit validation

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Closes https://github.com/espressif/esp-idf/issues/17530
This commit is contained in:
Guilherme Ferreira
2026-04-21 09:51:14 +02:00
committed by Euripedes Rocha
parent ad743ae44a
commit 2716f9ff65
1 changed files with 1 additions and 1 deletions
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components/esp_eth/src/spi/w5500/esp_eth_mac_w5500.c
+1 -1
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@@ -544,7 +544,7 @@ static inline bool is_w5500_sane_for_rxtx(emac_w5500_t *emac)
{
uint8_t phycfg;
/* phy is ok for rx and tx operations if bits RST and LNK are set (no link down, no reset) */
if (w5500_read(emac, W5500_REG_PHYCFGR, &phycfg, 1) == ESP_OK && (phycfg & 0x8001)) {
if (w5500_read(emac, W5500_REG_PHYCFGR, &phycfg, 1) == ESP_OK && (phycfg & 0x81) == 0x81) {
return true;
}
return false;