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feat: add i2s & etm sleep retention entry on H4

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This commit is contained in:
laokaiyao
2025-07-22 10:05:12 +08:00
parent 424991faaf
commit 263a056486
31 changed files with 317 additions and 233 deletions
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components/soc/esp32p4/include/soc/soc.h
-1
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@@ -19,7 +19,6 @@
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) // only one UHCI on C6
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
#define UART_FIFO_AHB_REG(i) (REG_UART_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
components/soc/esp32p4/register/hw_ver1/soc/i2s_reg.h
+2
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@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
/** I2S_INT_RAW_REG register
* I2S interrupt raw register, valid in level.
*/