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rtc: united sar peripheral control

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This commit is contained in:
Armando
2022-10-27 16:51:25 +08:00
parent bd18096cb4
commit 260ee86c37
29 changed files with 733 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/include/esp_private/sar_periph_ctrl.h
+29
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* See target/sar_periph_ctrl.c to know involved peripherals
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* Initialise SAR related peripheral register settings
* Should only be used when running into app stage
*/
void sar_periph_ctrl_init(void);
#ifdef __cplusplus
}
#endif
components/esp_hw_support/port/esp32/CMakeLists.txt
+2 -1
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@@ -11,7 +11,8 @@ set(srcs
"chip_info.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "cache_sram_mmu.c")
list(APPEND srcs "cache_sram_mmu.c"
"sar_periph_ctrl.c")
endif()
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
components/esp_hw_support/port/esp32/rtc_init.c
+8
View File
@@ -12,6 +12,9 @@
#include "soc/dport_reg.h"
#include "hal/efuse_ll.h"
#include "soc/gpio_periph.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
void rtc_init(rtc_config_t cfg)
@@ -94,6 +97,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
components/esp_hw_support/port/esp32/sar_periph_ctrl.c
+37
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@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to ON state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
components/esp_hw_support/port/esp32c2/CMakeLists.txt
+7 -2
View File
@@ -4,8 +4,13 @@ set(srcs "rtc_clk_init.c"
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"chip_info.c"
)
"chip_info.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "sar_periph_ctrl.c")
endif()
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
components/esp_hw_support/port/esp32c2/rtc_init.c
+8
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@@ -21,6 +21,9 @@
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
static const char *TAG = "rtc_init";
@@ -121,6 +124,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c
+38
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@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
components/esp_hw_support/port/esp32c3/CMakeLists.txt
+3 -3
View File
@@ -4,12 +4,12 @@ set(srcs "rtc_clk_init.c"
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"chip_info.c"
)
"chip_info.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "esp_crypto_lock.c"
"esp_ds.c")
"esp_ds.c"
"sar_periph_ctrl.c")
# init constructor for wifi
list(APPEND srcs "adc2_init_cal.c")
components/esp_hw_support/port/esp32c3/rtc_init.c
+8
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@@ -21,6 +21,9 @@
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
static const char *TAG = "rtc_init";
@@ -156,6 +159,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 1);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c
+38
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@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
components/esp_hw_support/port/esp32c6/CMakeLists.txt
+2 -2
View File
@@ -4,13 +4,13 @@ set(srcs "rtc_clk_init.c"
# "rtc_pm.c" // TODO: IDF-5645
# "rtc_sleep.c" // TODO: IDF-5645
"rtc_time.c"
"chip_info.c"
)
"chip_info.c")
if(NOT BOOTLOADER_BUILD)
# list(APPEND srcs "esp_hmac.c" // TODO: IDF-5355
# "esp_crypto_lock.c"
# "esp_ds.c") // TODO: IDF-5360
list(APPEND srcs "sar_periph_ctrl.c")
if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c
+29
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
void sar_periph_ctrl_init(void)
{
//TODO: IDF-6124
}
void sar_periph_ctrl_power_disable(void)
{
//TODO: IDF-6124
}
components/esp_hw_support/port/esp32h2/CMakeLists.txt
+3 -3
View File
@@ -4,12 +4,12 @@ set(srcs "rtc_clk_init.c"
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"chip_info.c"
)
"chip_info.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "esp_crypto_lock.c"
"esp_ds.c")
"esp_ds.c"
"sar_periph_ctrl.c")
if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
components/esp_hw_support/port/esp32h2/rtc_init.c
+8
View File
@@ -20,6 +20,9 @@
#include "esp_efuse_table.h"
#include "i2c_pmu.h"
#include "soc/clkrst_reg.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
void pmu_ctl(void);
void dcdc_ctl(uint32_t mode);
@@ -135,6 +138,11 @@ void rtc_init(rtc_config_t cfg)
}
/* config dcdc frequency */
REG_SET_FIELD(RTC_CNTL_DCDC_CTRL0_REG, RTC_CNTL_FSW_DCDC, RTC_CNTL_DCDC_FREQ_DEFAULT);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
void pmu_ctl(void)
components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c
+30
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
void sar_periph_ctrl_init(void)
{
//TODO: IDF-6123
}
void sar_periph_ctrl_power_disable(void)
{
//TODO: IDF-6123
}
components/esp_hw_support/port/esp32s2/CMakeLists.txt
+3 -3
View File
@@ -8,13 +8,13 @@ set(srcs
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"chip_info.c"
)
"chip_info.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "memprot.c"
"esp_crypto_lock.c"
"esp_ds.c")
"esp_ds.c"
"sar_periph_ctrl.c")
# init constructor for wifi
list(APPEND srcs "adc2_init_cal.c")
components/esp_hw_support/port/esp32s2/rtc_init.c
+8
View File
@@ -18,6 +18,9 @@
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
__attribute__((unused)) static const char *TAG = "rtc_init";
@@ -163,6 +166,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c
+38
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@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}
components/esp_hw_support/port/esp32s3/CMakeLists.txt
+3 -3
View File
@@ -8,12 +8,12 @@ set(srcs
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"chip_info.c"
)
"chip_info.c")
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "esp_ds.c"
"esp_crypto_lock.c")
"esp_crypto_lock.c"
"sar_periph_ctrl.c")
if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
components/esp_hw_support/port/esp32s3/rtc_init.c
+8
View File
@@ -25,6 +25,9 @@
#include "esp_efuse_table.h"
#include "esp_private/spi_flash_os.h"
#include "hal/efuse_hal.h"
#ifndef BOOTLOADER_BUILD
#include "esp_private/sar_periph_ctrl.h"
#endif
#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
@@ -196,6 +199,11 @@ void rtc_init(rtc_config_t cfg)
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
#ifndef BOOTLOADER_BUILD
//initialise SAR related peripheral register settings
sar_periph_ctrl_init();
#endif
}
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c
+38
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@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* SAR related peripherals are interdependent. This file
* provides a united control to these registers, as multiple
* components require these controls.
*
* Related peripherals are:
* - ADC
* - PWDET
* - Temp Sensor
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/sar_periph_ctrl.h"
#include "hal/sar_ctrl_ll.h"
extern portMUX_TYPE rtc_spinlock;
void sar_periph_ctrl_init(void)
{
//Put SAR control mux to FSM state
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
//Add other periph power control initialisation here
}
void sar_periph_ctrl_power_disable(void)
{
portENTER_CRITICAL_SAFE(&rtc_spinlock);
sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_OFF);
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
}