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fix(ll): fix cpp compile error

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Merges https://github.com/espressif/esp-idf/pull/12093

fix(ll): remove FLAG_ATTR macro

Such kind of operator overload will not work because C++ thinks such overload is ambiguous and it still prefer the built-in one which accepts and returns integer. Manually force type conversion seems to be unavoidable.
This commit is contained in:
Planck (Lu Zeyu)
2023-09-14 14:48:12 +08:00
parent 3717963618
commit 255d499884
114 changed files with 623 additions and 564 deletions
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components/hal/esp32s2/include/hal/aes_ll.h
+1 -1
View File
@@ -123,7 +123,7 @@ static inline void aes_ll_cont_transform(void)
*/
static inline esp_aes_state_t aes_ll_get_state(void)
{
return REG_READ(AES_STATE_REG);
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}
components/hal/esp32s2/include/hal/cache_ll.h
+34 -34
View File
@@ -418,35 +418,35 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
{
(void)cache_id;
cache_bus_mask_t mask = 0;
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS1;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DRAM1_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS1;
mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS2;
mask |= (vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS2);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else if (vaddr_start >= SOC_DROM0_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS2;
mask |= (vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0;
mask |= (vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
} else {
abort();
}
@@ -468,15 +468,15 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
(void)cache_id;
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
}
@@ -492,15 +492,15 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
(void)cache_id;
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
}
components/hal/esp32s2/include/hal/dedic_gpio_ll.h
+1 -1
View File
@@ -31,8 +31,8 @@ static inline void dedic_gpio_ll_write_all(dedic_dev_t *dev, uint32_t value)
static inline void dedic_gpio_ll_write_mask(dedic_dev_t *dev, uint32_t channel_mask, uint32_t value)
{
dedic_gpio_out_msk_reg_t d = {
.gpio_out_value = value,
.gpio_out_msk = channel_mask,
.gpio_out_value = value
};
dev->gpio_out_msk.val = d.val;
}
components/hal/esp32s2/include/hal/gpspi_flash_ll.h
+9 -7
View File
@@ -175,12 +175,12 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@@ -209,8 +209,10 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->user) user = dev->user;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
@@ -242,8 +244,8 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
abort();
}
dev->ctrl = ctrl;
dev->user = user;
dev->ctrl.val = ctrl.val;
dev->user.val = user.val;
}
/**
@@ -296,7 +298,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**
components/hal/esp32s2/include/hal/i2c_ll.h
+7 -5
View File
@@ -13,13 +13,13 @@
#include "soc/clk_tree_defs.h"
#include "hal/i2c_types.h"
#include "esp_attr.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief I2C hardware cmd register fields.
*/
@@ -815,7 +815,8 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
__attribute__((always_inline))
static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.arbitration_lost) {
*event = I2C_INTR_EVENT_ARBIT_LOST;
} else if (int_sts.nack) {
@@ -842,7 +843,8 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
__attribute__((always_inline))
static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
{
typeof(hw->int_status) int_sts = hw->int_status;
typeof(hw->int_status) int_sts;
int_sts.val = hw->int_status.val;
if (int_sts.tx_fifo_wm) {
*event = I2C_INTR_EVENT_TXFIFO_EMPTY;
} else if (int_sts.trans_complete) {
@@ -984,8 +986,8 @@ static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int lo
*/
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
{
*tx_mode = hw->ctr.tx_lsb_first;
*rx_mode = hw->ctr.rx_lsb_first;
*tx_mode = (i2c_trans_mode_t)(hw->ctr.tx_lsb_first);
*rx_mode = (i2c_trans_mode_t)(hw->ctr.rx_lsb_first);
}
/**
components/hal/esp32s2/include/hal/ledc_ll.h
+1 -1
View File
@@ -538,7 +538,7 @@ static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_
*/
static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
{
*timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel;
*timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
}
#ifdef __cplusplus
components/hal/esp32s2/include/hal/memprot_peri_ll.h
+1
View File
@@ -11,6 +11,7 @@
#include "soc/dport_access.h"
#include "soc/periph_defs.h"
#include "hal/memprot_types.h"
#include "hal/memprot_ll.h"
#ifdef __cplusplus
extern "C" {
components/hal/esp32s2/include/hal/mpi_ll.h
+2
View File
@@ -7,6 +7,7 @@
#include <stdbool.h>
#include <string.h>
#include <sys/param.h>
#include "hal/assert.h"
#include "hal/mpi_types.h"
#include "soc/hwcrypto_periph.h"
@@ -17,6 +18,7 @@
extern "C" {
#endif
static inline size_t mpi_ll_calculate_hardware_words(size_t words)
{
return words;
components/hal/esp32s2/include/hal/pcnt_ll.h
+25 -11
View File
@@ -92,7 +92,9 @@ static inline void pcnt_ll_set_level_action(pcnt_dev_t *hw, uint32_t unit, uint3
__attribute__((always_inline))
static inline int pcnt_ll_get_count(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_cnt_reg_t cnt_reg = hw->cnt_unit[unit];
pcnt_un_cnt_reg_t cnt_reg;
cnt_reg.val = hw->cnt_unit[unit].val;
int16_t value = cnt_reg.pulse_cnt_un;
return value;
}
@@ -248,9 +250,11 @@ static inline void pcnt_ll_disable_all_events(pcnt_dev_t *hw, uint32_t unit)
*/
static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_h_lim_un = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@@ -262,9 +266,11 @@ static inline void pcnt_ll_set_high_limit_value(pcnt_dev_t *hw, uint32_t unit, i
*/
static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, int value)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
conf2_reg.cnt_l_lim_un = value;
hw->conf_unit[unit].conf2 = conf2_reg;
hw->conf_unit[unit].conf2.val = conf2_reg.val;
}
/**
@@ -277,13 +283,15 @@ static inline void pcnt_ll_set_low_limit_value(pcnt_dev_t *hw, uint32_t unit, in
*/
static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres, int value)
{
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
conf1_reg.cnt_thres0_un = value;
} else {
conf1_reg.cnt_thres1_un = value;
}
hw->conf_unit[unit].conf1 = conf1_reg;
hw->conf_unit[unit].conf1.val = conf1_reg.val;
}
/**
@@ -295,7 +303,9 @@ static inline void pcnt_ll_set_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32
*/
static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_h_lim_un;
return value;
}
@@ -309,7 +319,9 @@ static inline int pcnt_ll_get_high_limit_value(pcnt_dev_t *hw, uint32_t unit)
*/
static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
{
pcnt_un_conf2_reg_t conf2_reg = hw->conf_unit[unit].conf2;
pcnt_un_conf2_reg_t conf2_reg;
conf2_reg.val = hw->conf_unit[unit].conf2.val;
int16_t value = conf2_reg.cnt_l_lim_un;
return value;
}
@@ -325,7 +337,9 @@ static inline int pcnt_ll_get_low_limit_value(pcnt_dev_t *hw, uint32_t unit)
static inline int pcnt_ll_get_thres_value(pcnt_dev_t *hw, uint32_t unit, uint32_t thres)
{
int16_t value;
pcnt_un_conf1_reg_t conf1_reg = hw->conf_unit[unit].conf1;
pcnt_un_conf1_reg_t conf1_reg;
conf1_reg.val = hw->conf_unit[unit].conf1.val;
if (thres == 0) {
value = conf1_reg.cnt_thres0_un;
} else {
@@ -356,7 +370,7 @@ static inline uint32_t pcnt_ll_get_unit_status(pcnt_dev_t *hw, uint32_t unit)
__attribute__((always_inline))
static inline pcnt_unit_zero_cross_mode_t pcnt_ll_get_zero_cross_mode(pcnt_dev_t *hw, uint32_t unit)
{
return hw->status_unit[unit].val & 0x03;
return (pcnt_unit_zero_cross_mode_t)(hw->status_unit[unit].val & 0x03);
}
/**
components/hal/esp32s2/include/hal/spi_ll.h
-2
View File
@@ -73,7 +73,6 @@ typedef enum {
SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
SPI_LL_INTR_SEG_DONE = BIT(14),
} spi_ll_intr_t;
FLAG_ATTR(spi_ll_intr_t)
///< Flags for conditions under which the transaction length should be recorded
typedef enum {
@@ -82,7 +81,6 @@ typedef enum {
SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
} spi_ll_trans_len_cond_t;
FLAG_ATTR(spi_ll_trans_len_cond_t)
// SPI base command in esp32s2
typedef enum {
components/hal/esp32s2/include/hal/spimem_flash_ll.h
+6 -5
View File
@@ -339,12 +339,12 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
.usr_command = 1,
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
.usr_command = 1,
};
dev->user = user;
dev->user.val = user.val;
}
/*------------------------------------------------------------------------------
* Configs
@@ -369,7 +369,8 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl = dev->ctrl;
typeof (dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
switch (read_mode) {
@@ -394,7 +395,7 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
default:
abort();
}
dev->ctrl = ctrl;
dev->ctrl.val = ctrl.val;
}
/**
@@ -447,7 +448,7 @@ static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t comm
.usr_command_value = command,
.usr_command_bitlen = (bitlen - 1),
};
dev->user2 = user2;
dev->user2.val = user2.val;
}
/**
components/hal/esp32s2/include/hal/touch_sensor_ll.h
+10 -10
View File
@@ -460,7 +460,7 @@ static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type)
*/
static inline void touch_ll_get_idle_channel_connect(touch_pad_conn_type_t *type)
{
*type = RTCCNTL.touch_scan_ctrl.touch_inactive_connection;
*type = (touch_pad_conn_type_t)(RTCCNTL.touch_scan_ctrl.touch_inactive_connection);
}
/**
@@ -707,7 +707,7 @@ static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
*/
static inline void touch_ll_filter_get_smooth_mode(touch_smooth_mode_t *mode)
{
*mode = RTCCNTL.touch_filter_ctrl.touch_smooth_lvl;
*mode = (touch_smooth_mode_t)(RTCCNTL.touch_filter_ctrl.touch_smooth_lvl);
}
/**
@@ -849,7 +849,7 @@ static inline void touch_ll_denoise_set_cap_level(touch_pad_denoise_cap_t cap_le
*/
static inline void touch_ll_denoise_get_cap_level(touch_pad_denoise_cap_t *cap_level)
{
*cap_level = RTCCNTL.touch_ctrl2.touch_refc;
*cap_level = (touch_pad_denoise_cap_t)(RTCCNTL.touch_ctrl2.touch_refc);
}
/**
@@ -871,7 +871,7 @@ static inline void touch_ll_denoise_set_grade(touch_pad_denoise_grade_t grade)
*/
static inline void touch_ll_denoise_get_grade(touch_pad_denoise_grade_t *grade)
{
*grade = RTCCNTL.touch_scan_ctrl.touch_denoise_res;
*grade = (touch_pad_denoise_grade_t)(RTCCNTL.touch_scan_ctrl.touch_denoise_res);
}
/**
@@ -903,7 +903,7 @@ static inline void touch_ll_waterproof_set_guard_pad(touch_pad_t pad_num)
*/
static inline void touch_ll_waterproof_get_guard_pad(touch_pad_t *pad_num)
{
*pad_num = RTCCNTL.touch_scan_ctrl.touch_out_ring;
*pad_num = (touch_pad_t)(RTCCNTL.touch_scan_ctrl.touch_out_ring);
}
/**
@@ -927,7 +927,7 @@ static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver
*/
static inline void touch_ll_waterproof_get_sheild_driver(touch_pad_shield_driver_t *driver_level)
{
*driver_level = RTCCNTL.touch_scan_ctrl.touch_bufdrv;
*driver_level = (touch_pad_shield_driver_t)(RTCCNTL.touch_scan_ctrl.touch_bufdrv);
}
/**
@@ -974,9 +974,9 @@ static inline void touch_ll_proximity_set_channel_num(const touch_pad_t prox_pad
*/
static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[])
{
prox_pad[0] = SENS.sar_touch_conf.touch_approach_pad0;
prox_pad[1] = SENS.sar_touch_conf.touch_approach_pad1;
prox_pad[2] = SENS.sar_touch_conf.touch_approach_pad2;
prox_pad[0] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad0);
prox_pad[1] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad1);
prox_pad[2] = (touch_pad_t)(SENS.sar_touch_conf.touch_approach_pad2);
}
/**
@@ -1052,7 +1052,7 @@ static inline void touch_ll_sleep_set_channel_num(touch_pad_t touch_num)
*/
static inline void touch_ll_sleep_get_channel_num(touch_pad_t *touch_num)
{
*touch_num = RTCCNTL.touch_slp_thres.touch_slp_pad;
*touch_num = (touch_pad_t)(RTCCNTL.touch_slp_thres.touch_slp_pad);
}
/**
components/hal/esp32s2/include/hal/uart_ll.h
+2 -2
View File
@@ -143,7 +143,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
*/
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
hw->int_ena.val = hw->int_ena.val | mask;
}
/**
@@ -156,7 +156,7 @@ FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*/
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
hw->int_ena.val = hw->int_ena.val & (~mask);
}
/**
components/hal/esp32s2/include/hal/usb_ll.h
+3 -2
View File
@@ -28,13 +28,14 @@ static inline void usb_ll_ext_phy_enable(void)
static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
{
usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
usb_wrap_otg_conf_reg_t conf;
conf.val = USB_WRAP.otg_conf.val;
conf.pad_pull_override = 1;
conf.dp_pullup = dp_pu;
conf.dp_pulldown = dp_pd;
conf.dm_pullup = dm_pu;
conf.dm_pulldown = dm_pd;
USB_WRAP.otg_conf = conf;
USB_WRAP.otg_conf.val = conf.val;
}
#ifdef __cplusplus
components/hal/esp32s2/include/hal/usb_phy_ll.h
+3 -2
View File
@@ -49,13 +49,14 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
*/
static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
{
usb_wrap_otg_conf_reg_t conf = hw->otg_conf;
usb_wrap_otg_conf_reg_t conf;
conf.val = hw->otg_conf.val;
conf.pad_pull_override = 1;
conf.dp_pullup = dp_pu;
conf.dp_pulldown = dp_pd;
conf.dm_pullup = dm_pu;
conf.dm_pulldown = dm_pd;
hw->otg_conf = conf;
hw->otg_conf.val = conf.val;
}
/**