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ci(i2s): fixed occationally failure on P4

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read write case can sometimes failed due to the low frequency of the default I2S clock source on P4.
This commit is contained in:
laokaiyao
2025-11-06 10:46:36 +08:00
committed by Kevin (Lao Kaiyao)
parent 616ff5862b
commit 243ff5d5f6
4 changed files with 30 additions and 7 deletions
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components/esp_driver_i2s/i2s_common.c
+5
View File
@@ -568,6 +568,11 @@ uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz)
if (clk_src == I2S_CLK_SRC_APLL) {
return i2s_set_get_apll_freq(mclk_freq_hz);
}
#endif
#ifdef I2S_LL_DEFAULT_CLK_SRC
if (clk_src == I2S_CLK_SRC_DEFAULT) {
clk_src = I2S_LL_DEFAULT_CLK_SRC;
}
#endif
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq);
return clk_freq;
components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c
+4 -4
View File
@@ -632,7 +632,7 @@ TEST_CASE("I2S_loopback_test", "[i2s]")
TEST_ESP_OK(i2s_del_channel(rx_handle));
}
#if SOC_I2S_NUM > 1
#if SOC_I2S_NUM > 1 && !CONFIG_IDF_TARGET_ESP32P4
TEST_CASE("I2S_master_write_slave_read_test", "[i2s]")
{
i2s_chan_handle_t tx_handle;
@@ -798,10 +798,10 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]")
TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
// ESP32-P4 has no PLL except XTAL
#if !CONFIG_IDF_TARGET_ESP32P4
#ifdef I2S_LL_DEFAULT_CLK_SRC
std_cfg.clk_cfg.clk_src = I2S_LL_DEFAULT_CLK_SRC;
#endif
i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);
#endif // CONFIG_IDF_TARGET_ESP32P4
#if SOC_I2S_SUPPORTS_XTAL
std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_XTAL;
i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);