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refactor(soc): reformat code with astyle

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This commit is contained in:
morris
2024-11-22 11:09:38 +08:00
parent 32905aa39e
commit 24272610b2
181 changed files with 1984 additions and 2106 deletions
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components/soc/esp32c2/include/soc/clk_tree_defs.h
-1
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@@ -268,7 +268,6 @@ typedef enum {
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
/**
components/soc/esp32c2/include/soc/clkout_channel.h
-1
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@@ -26,7 +26,6 @@ typedef enum clock_out_channel {
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
#define CLKOUT_CHANNEL_MASK(channel) ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
(channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
(channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
components/soc/esp32c2/include/soc/ext_mem_defs.h
+1 -4
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@@ -5,7 +5,6 @@
*/
#pragma once
#include <stdint.h>
#include "esp_bit_defs.h"
@@ -21,7 +20,6 @@ extern "C" {
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define SOC_IRAM0_ADDRESS_LOW 0x4037C000
#define SOC_IRAM0_ADDRESS_HIGH 0x403C0000
@@ -58,7 +56,7 @@ extern "C" {
* valid bit + value bits
* valid bit is BIT(6), so value bits are 0x3f
*/
#define SOC_MMU_VALID_VAL_MASK 0x3f
#define SOC_MMU_VALID_VAL_MASK 0x3f
/**
* Max MMU available paddr page num.
@@ -134,7 +132,6 @@ extern "C" {
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
#endif
/**
* ROM flash mmap driver needs below definitions
*/
components/soc/esp32c2/include/soc/gpio_pins.h
-1
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@@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
components/soc/esp32c2/include/soc/regi2c_defs.h
-2
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@@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
@@ -22,7 +21,6 @@
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_CONFIG2_REG 0x6004E848
#define ANA_CONFIG2_M BIT(18)
components/soc/esp32c2/include/soc/reset_reasons.h
-1
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@@ -43,7 +43,6 @@ typedef enum {
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif
components/soc/esp32c2/include/soc/soc.h
-1
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@@ -23,7 +23,6 @@
0 \
)
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)