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Merge branch 'fix/esp32_adc_continuous_loss_sample' into 'master'

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Fix/esp32 adc continuous loss sample

Closes IDFGH-9225, IDF-8427, and FCS-1773

See merge request espressif/esp-idf!41933
This commit is contained in:
Gao Xu
2025-10-23 12:50:06 +08:00
parent 920efaabbd 97a3b51d11
commit 23dc9a9f47
10 changed files with 17 additions and 10 deletions
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components/hal/esp32/include/hal/adc_ll.h
+5 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,7 @@
#pragma once
#include <stdbool.h>
#include "esp_rom_sys.h"
#include "hal/adc_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
@@ -48,7 +49,7 @@ extern "C" {
//On esp32, ADC can only be continuously triggered when `ADC_LL_DEFAULT_CONV_LIMIT_EN == 1`, `ADC_LL_DEFAULT_CONV_LIMIT_NUM != 0`
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 1
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 255
/*---------------------------------------------------------------
PWDET (Power Detect)
@@ -158,6 +159,8 @@ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
*/
static inline void adc_ll_digi_convert_limit_enable(bool enable)
{
//ESP32 has a hardware limitaton, meas_num_limit can only be cleared after ADC enters sample phase(10~15us after start)
esp_rom_delay_us(60);
SYSCON.saradc_ctrl2.meas_num_limit = enable;
}