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Merge branch 'feat/esp_tee_mspi_tuning_v6.0' into 'release/v6.0'
change(esp_tee): Fix TEE SPI flash API issues on ESP32-C5 (v6.0) See merge request espressif/esp-idf!42906
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@@ -6,7 +6,7 @@ set(includes "include" "${target}/include")
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if(esp_tee_build)
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if(CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1)
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list(APPEND srcs "spi_flash_hal.c")
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list(APPEND srcs "spi_flash_hal.c" "spi_flash_hal_iram.c")
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endif()
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elseif(NOT BOOTLOADER_BUILD)
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if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
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@@ -131,15 +131,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
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addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
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#endif
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spi_flash_ll_set_extra_address(dev, 0);
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// TODO: [IDF-13582]
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// Currently, REE and TEE use different sets of APIs for flash operations -
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// REE uses the IDF SPI flash driver while TEE call the ROM APIs. This inconsistency
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// leads to compatibility issues on ESP32-C5.
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// One specific issue arises when esp_flash_read() is used in REE, which internally
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// calls spi_flash_ll_wb_mode_enable(). This function enables the WB mode bit in
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// the flash write operation. However, the ROM API does not support this
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// feature, resulting in failures when TEE attempts to access flash after this call.
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#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL && !CONFIG_SECURE_ENABLE_TEE
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#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
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spi_flash_ll_wb_mode_enable(dev, true);
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#endif
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}
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@@ -218,8 +210,7 @@ esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_tr
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if (trans->miso_len > 0) {
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spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len);
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}
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// TODO: [IDF-13582]
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#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL && !CONFIG_SECURE_ENABLE_TEE
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#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
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spi_flash_ll_wb_mode_enable(dev, false);
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#endif
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return ESP_OK;
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