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fix(esp_rom): implement cache writeback related apis in iram

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avoid critical issues caused by manual cache writeback and conflicting
writes. The issue exist on chips after esp32p4
This commit is contained in:
wanglei
2026-05-22 10:16:02 +08:00
parent 8f3d8b41c3
commit 1f559a5558
19 changed files with 273 additions and 25 deletions
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components/esp_rom/esp32h4/Kconfig.soc_caps.in
+4
View File
@@ -78,3 +78,7 @@ config ESP_ROM_WDT_INIT_PATCH
config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
bool
default y
config ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP
bool
default y
components/esp_rom/esp32h4/esp_rom_caps.h
+1
View File
@@ -25,3 +25,4 @@
#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock
#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
#define ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP (1) // ROM cache writeback related needs patch to avoid sync loss, no map parameter
components/esp_rom/esp32h4/ld/esp32h4.rom.ld
+5 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -182,12 +182,12 @@ Cache_Sync_Items = 0x400005b8;
Cache_Op_Addr = 0x400005bc;
Cache_Invalidate_Addr = 0x400005c0;
Cache_Clean_Addr = 0x400005c4;
Cache_WriteBack_Addr = 0x400005c8;
Cache_WriteBack_Invalidate_Addr = 0x400005cc;
PROVIDE( Cache_WriteBack_Addr = 0x400005c8 );
PROVIDE( Cache_WriteBack_Invalidate_Addr = 0x400005cc );
Cache_Invalidate_All = 0x400005d0;
Cache_Clean_All = 0x400005d4;
Cache_WriteBack_All = 0x400005d8;
Cache_WriteBack_Invalidate_All = 0x400005dc;
PROVIDE( Cache_WriteBack_All = 0x400005d8 );
PROVIDE( Cache_WriteBack_Invalidate_All = 0x400005dc );
Cache_Mask_All = 0x400005e0;
Cache_UnMask_Dram0 = 0x400005e4;
Cache_Suspend_Autoload = 0x400005e8;