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Merge branch 'feature/esp32p4_eco5_support_v5.4' into 'release/v5.4'

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feat(gpio/ledc/uart/2ddma/ppa): ESP32P4 ECO5 related updates (v5.4)

See merge request espressif/esp-idf!42819
This commit is contained in:
morris
2025-11-18 17:17:43 +08:00
parent bd11845900 0c243c9490
commit 1e975c6be2
49 changed files with 4445 additions and 19668 deletions
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components/hal/esp32p4/include/hal/dma2d_ll.h
+80 -104
View File
@@ -11,8 +11,10 @@
#include "hal/dma2d_types.h"
#include "soc/dma2d_channel.h"
#include "soc/dma2d_struct.h"
#include "soc/soc_caps.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/config.h"
#include "soc/soc.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -22,6 +24,14 @@ extern "C" {
#define DMA2D_LL_GET_HW(id) (((id) == 0) ? (&DMA2D) : NULL)
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define DMA2D_LL_TX_CHANNELS_PER_GROUP SOC_DMA2D_TX_CHANNELS_PER_GROUP // Number of 2D-DMA TX (OUT) channels in each group
#define DMA2D_LL_RX_CHANNELS_PER_GROUP SOC_DMA2D_RX_CHANNELS_PER_GROUP // Number of 2D-DMA RX (IN) channels in each group
#else
#define DMA2D_LL_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group
#define DMA2D_LL_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group
#endif
// 2D-DMA interrupts
#define DMA2D_LL_RX_EVENT_MASK (0x3FFF)
#define DMA2D_LL_TX_EVENT_MASK (0x1FFF)
@@ -57,8 +67,11 @@ extern "C" {
// Bit masks that are used to indicate availability of some sub-features in the channels
#define DMA2D_LL_TX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // TX channels that support reorder feature
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2 | BIT3) // TX channels that support color space conversion feature
#else
#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2) // TX channels that support color space conversion feature
#endif
#define DMA2D_LL_RX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // RX channels that support reorder feature
#define DMA2D_LL_RX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0) // RX channels that support color space conversion feature
@@ -158,16 +171,13 @@ static inline uint32_t dma2d_ll_get_scramble_order_sel(dma2d_scramble_order_t or
}
/////////////////////////////////////// RX ///////////////////////////////////////////
#define DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, ch, reg) ((volatile void*[]){&dev->in_channel0.reg, &dev->in_channel1.reg}[(ch)])
/**
* @brief Get 2D-DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_int_st_chn_reg_t *reg = (volatile dma2d_in_int_st_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st);
return reg->val;
return dev->in_channel[channel].in_int_st.val & DMA2D_LL_RX_EVENT_MASK;
}
/**
@@ -176,11 +186,10 @@ static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
volatile dma2d_in_int_ena_chn_reg_t *reg = (volatile dma2d_in_int_ena_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_ena);
if (enable) {
reg->val = reg->val | (mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val | (mask & DMA2D_LL_RX_EVENT_MASK);
} else {
reg->val = reg->val & ~(mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val & ~(mask & DMA2D_LL_RX_EVENT_MASK);
}
}
@@ -190,8 +199,7 @@ static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t chann
__attribute__((always_inline))
static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t channel, uint32_t mask)
{
volatile dma2d_in_int_clr_chn_reg_t *reg = (volatile dma2d_in_int_clr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_clr);
reg->val = (mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_clr.val = (mask & DMA2D_LL_RX_EVENT_MASK);
}
/**
@@ -199,7 +207,7 @@ static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t
*/
static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *dev, uint32_t channel)
{
return (volatile void *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st);
return (volatile void *)(&dev->in_channel[channel].in_int_st);
}
/**
@@ -208,8 +216,7 @@ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *d
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_check_owner_chn = enable;
dev->in_channel[channel].in_conf0.in_check_owner_chn = enable;
}
/**
@@ -218,8 +225,7 @@ static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t cha
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_page_bound_en_chn = enable;
dev->in_channel[channel].in_conf0.in_page_bound_en_chn = enable;
}
/**
@@ -249,8 +255,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t
// Unsupported data burst length
abort();
}
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_mem_burst_length_chn = sel;
dev->in_channel[channel].in_conf0.in_mem_burst_length_chn = sel;
}
/**
@@ -259,8 +264,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->indscr_burst_en_chn = enable;
dev->in_channel[channel].in_conf0.indscr_burst_en_chn = enable;
}
/**
@@ -269,9 +273,8 @@ static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_
__attribute__((always_inline))
static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_rst_chn = 1;
reg->in_rst_chn = 0;
dev->in_channel[channel].in_conf0.in_rst_chn = 1;
dev->in_channel[channel].in_conf0.in_rst_chn = 0;
}
/**
@@ -280,8 +283,7 @@ static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state);
return reg->in_reset_avail_chn;
return dev->in_channel[channel].in_state.in_reset_avail_chn;
}
/**
@@ -290,8 +292,7 @@ static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel
__attribute__((always_inline))
static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool disable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_cmd_disable_chn = disable;
dev->in_channel[channel].in_conf0.in_cmd_disable_chn = disable;
}
/**
@@ -300,8 +301,7 @@ static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool di
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_dscr_port(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_dscr_port_en_chn = enable;
dev->in_channel[channel].in_conf0.in_dscr_port_en_chn = enable;
}
/**
@@ -328,8 +328,7 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c
// Unsupported macro block size
abort();
}
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_macro_block_size_chn = sel;
dev->in_channel[channel].in_conf0.in_macro_block_size_chn = sel;
}
/**
@@ -338,9 +337,8 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_pop_chn_reg_t *reg = (volatile dma2d_in_pop_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_pop);
reg->infifo_pop_chn = 1;
return reg->infifo_rdata_chn;
dev->in_channel[channel].in_pop.infifo_pop_chn = 1;
return dev->in_channel[channel].in_pop.infifo_rdata_chn;
}
/**
@@ -349,8 +347,7 @@ static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile dma2d_in_link_addr_chn_reg_t *reg = (volatile dma2d_in_link_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_addr);
reg->inlink_addr_chn = addr;
dev->in_channel[channel].in_link_addr.inlink_addr_chn = addr;
}
/**
@@ -359,8 +356,7 @@ static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel,
__attribute__((always_inline))
static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_start_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_start_chn = 1;
}
/**
@@ -369,8 +365,7 @@ static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_stop_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_stop_chn = 1;
}
/**
@@ -379,8 +374,7 @@ static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_restart_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_restart_chn = 1;
}
/**
@@ -389,8 +383,7 @@ static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t channel, int owner)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_auto_ret_chn = owner;
dev->in_channel[channel].in_link_conf.inlink_auto_ret_chn = owner;
}
/**
@@ -399,8 +392,7 @@ static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
return reg->inlink_park_chn;
return dev->in_channel[channel].in_link_conf.inlink_park_chn;
}
/**
@@ -409,8 +401,7 @@ static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t chann
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state);
return (reg->in_state_chn == 0);
return (dev->in_channel[channel].in_state.in_state_chn == 0);
}
/**
@@ -419,8 +410,7 @@ static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_suc_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_suc_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_suc_eof_des_addr);
return reg->val;
return dev->in_channel[channel].in_suc_eof_des_addr.val;
}
/**
@@ -429,8 +419,7 @@ static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, u
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_err_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_err_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_err_eof_des_addr);
return reg->val;
return dev->in_channel[channel].in_err_eof_des_addr.val;
}
/**
@@ -439,18 +428,7 @@ static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uin
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_prefetched_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_dscr_chn_reg_t *reg = (volatile dma2d_in_dscr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_dscr);
return reg->val;
}
/**
* @brief Set priority for 2D-DMA RX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_priority_chn = prio;
return dev->in_channel[channel].in_dscr.val;
}
/**
@@ -459,10 +437,8 @@ static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel,
__attribute__((always_inline))
static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t channel, dma2d_trigger_peripheral_t periph, int periph_id)
{
volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel);
peri_sel_reg->in_peri_sel_chn = periph_id;
volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
conf0_reg->in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M);
dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = periph_id;
dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M);
}
/**
@@ -471,10 +447,8 @@ static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t chan
__attribute__((always_inline))
static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel);
peri_sel_reg->in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE;
volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
conf0_reg->in_mem_trans_en_chn = false;
dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE;
dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = false;
}
// REORDER FUNCTION (Only CH0 supports this feature)
@@ -485,8 +459,7 @@ static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_reorder(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_reorder_en_chn = enable;
dev->in_channel[channel].in_conf0.in_reorder_en_chn = enable;
}
// COLOR SPACE CONVERSION FUNCTION
@@ -524,6 +497,17 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
proc_en = false;
output_sel = 1;
break;
case DMA2D_CSC_RX_YUV444_TO_YUV422:
input_sel = 0;
proc_en = false;
output_sel = 2;
break;
case DMA2D_CSC_RX_YUV444_TO_YUV420:
case DMA2D_CSC_RX_YUV422_TO_YUV420:
input_sel = 0;
proc_en = false;
output_sel = 3;
break;
case DMA2D_CSC_RX_YUV420_TO_RGB888_601:
case DMA2D_CSC_RX_YUV422_TO_RGB888_601:
input_sel = 0;
@@ -581,13 +565,13 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
abort();
}
dev->in_channel0.in_color_convert.in_color_input_sel_chn = input_sel;
dev->in_channel0.in_color_convert.in_color_3b_proc_en_chn = proc_en;
dev->in_channel0.in_color_convert.in_color_output_sel_chn = output_sel;
dev->in_channel[channel].in_color_convert.in_color_input_sel_chn = input_sel;
dev->in_channel[channel].in_color_convert.in_color_3b_proc_en_chn = proc_en;
dev->in_channel[channel].in_color_convert.in_color_output_sel_chn = output_sel;
if (proc_en) {
HAL_ASSERT(table);
typeof(dev->in_channel0.in_color_param_group) color_param_group;
typeof(dev->in_channel[channel].in_color_param_group) color_param_group;
color_param_group.param_h.a = table[0][0];
color_param_group.param_h.b = table[0][1];
@@ -604,12 +588,12 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
color_param_group.param_l.c = table[2][2];
color_param_group.param_l.d = table[2][3];
dev->in_channel0.in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0];
dev->in_channel0.in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1];
dev->in_channel0.in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0];
dev->in_channel0.in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1];
dev->in_channel0.in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0];
dev->in_channel0.in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1];
dev->in_channel[channel].in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0];
dev->in_channel[channel].in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1];
dev->in_channel[channel].in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0];
dev->in_channel[channel].in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1];
dev->in_channel[channel].in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0];
dev->in_channel[channel].in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1];
}
}
@@ -620,7 +604,7 @@ __attribute__((always_inline))
static inline void dma2d_ll_rx_set_csc_pre_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order)
{
HAL_ASSERT(channel == 0); // Only channel 0 supports scramble
dev->in_channel0.in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order);
dev->in_channel[channel].in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order);
}
/**
@@ -630,7 +614,7 @@ __attribute__((always_inline))
static inline void dma2d_ll_rx_set_csc_post_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order)
{
HAL_ASSERT(channel == 0); // Only channel 0 supports scramble
dev->in_channel0.in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order);
dev->in_channel[channel].in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order);
}
// Arbiter
@@ -659,8 +643,7 @@ static inline void dma2d_ll_rx_set_arb_timeout(dma2d_dev_t *dev, uint32_t timeou
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t channel, uint32_t token_num)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_token_num_chn = token_num;
dev->in_channel[channel].in_arb.in_arb_token_num_chn = token_num;
}
/**
@@ -669,20 +652,22 @@ static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t chan
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_arb_token_num(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
return reg->in_arb_token_num_chn;
return dev->in_channel[channel].in_arb.in_arb_token_num_chn;
}
/**
* @brief Set 2D-DMA RX channel arbiter priority
* @brief Set priority for 2D-DMA RX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_priority_chn = priority;
dev->in_channel[channel].in_arb.in_arb_priority_chn = priority;
}
// ETM
// note that in_ch1 in_etm_conf register addr is different before and after rev3 chip!
/////////////////////////////////////// TX ///////////////////////////////////////////
/**
* @brief Get 2D-DMA TX channel interrupt status word
@@ -954,15 +939,6 @@ static inline uint32_t dma2d_ll_tx_get_prefetched_desc_addr(dma2d_dev_t *dev, ui
return dev->out_channel[channel].out_dscr.val;
}
/**
* @brief Set priority for 2D-DMA TX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->out_channel[channel].out_arb.out_arb_priority_chn = prio;
}
/**
* @brief Connect 2D-DMA TX channel to a given peripheral
*/
@@ -1165,10 +1141,10 @@ static inline uint32_t dma2d_ll_tx_get_arb_token_num(dma2d_dev_t *dev, uint32_t
}
/**
* @brief Set 2D-DMA TX channel arbiter priority
* @brief Set priority for 2D-DMA TX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_tx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
{
dev->out_channel[channel].out_arb.out_arb_priority_chn = priority;
}
components/hal/esp32p4/include/hal/ledc_ll.h
+3 -4
View File
@@ -245,7 +245,6 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
{
// The target has no timer-specific clock source option
HAL_ASSERT(hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 0);
*clk_src = LEDC_SCLK;
}
@@ -365,7 +364,7 @@ static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_m
*/
static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val)
{
*duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty >> 4);
*duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty_r >> 4);
}
/**
@@ -406,7 +405,7 @@ static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t spee
*/
static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num)
{
hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num = range_num;
hw->chn_gamma_conf[channel_num].gamma_entry_num = range_num;
}
/**
@@ -421,7 +420,7 @@ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mo
*/
static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num)
{
*range_num = hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num;
*range_num = hw->chn_gamma_conf[channel_num].gamma_entry_num;
}
/**
components/hal/esp32p4/include/hal/ppa_ll.h
+428 -6
View File
@@ -14,6 +14,7 @@
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -27,9 +28,15 @@ extern "C" {
#define PPA_LL_SRM_SCALING_INT_MAX (PPA_SR_SCAL_X_INT_V + 1)
#define PPA_LL_SRM_SCALING_FRAG_MAX (PPA_SR_SCAL_X_FRAG_V + 1)
// TODO: On P4 ECO2, SRM block size needs update
#define PPA_LL_SRM_DEFAULT_BLOCK_SIZE 18 // 18 x 18 block size
#define PPA_LL_SRM_YUV420_BLOCK_SIZE 20 // 20 x 20 block size
/**
* @brief Enumeration of PPA SRM macro block size options
*/
typedef enum {
PPA_LL_SRM_MB_SIZE_16_16, /*!< SRM engine processes with a macro block size of 16 x 16 */
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
PPA_LL_SRM_MB_SIZE_32_32, /*!< SRM engine processes with a macro block size of 32 x 32 */
#endif
} ppa_ll_srm_mb_size_t;
/**
* @brief Enumeration of PPA blending mode
@@ -68,6 +75,29 @@ static inline void ppa_ll_reset_register(void)
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ppa_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ppa_ll_reset_register(__VA_ARGS__)
/**
* @brief Configure the RGB888 to GRAY8 color conversion coefficients for SRM and Blending (excluding Fill)
*
* The gray value is calculated as: gray = (r_coeff * R + g_coeff * G + b_coeff * B) >> 8
*
* @param dev Peripheral instance address
* @param r_coeff Coefficient for Red channel, range 0-255
* @param g_coeff Coefficient for Green channel, range 0-255
* @param b_coeff Coefficient for Blue channel, range 0-255
*/
static inline void ppa_ll_set_rgb2gray_coeff(ppa_dev_t *dev, uint8_t r_coeff, uint8_t g_coeff, uint8_t b_coeff)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
HAL_ASSERT((r_coeff + g_coeff + b_coeff == 256) && "Sum of RGB to GRAY coefficients must be 256");
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_r, r_coeff);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_g, g_coeff);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_b, b_coeff);
#else
// GRAY8 color mode is not supported by PPA hardware before P4 ECO5
abort();
#endif
}
///////////////////////// Scaling, Rotating, Mirroring (SRM) //////////////////////////////
/**
* @brief Reset PPA scaling-rotating-mirroring engine
@@ -169,6 +199,30 @@ static inline void ppa_ll_srm_start(ppa_dev_t *dev)
dev->sr_scal_rotate.scal_rotate_start = 1;
}
/**
* @brief Check if the given color mode is supported by PPA SRM engine
*
* @param color_mode One of the values in ppa_srm_color_mode_t
* @return true if supported; false if not supported
*/
static inline bool ppa_ll_srm_is_color_mode_supported(ppa_srm_color_mode_t color_mode)
{
switch (color_mode) {
case PPA_SRM_COLOR_MODE_ARGB8888:
case PPA_SRM_COLOR_MODE_RGB888:
case PPA_SRM_COLOR_MODE_RGB565:
case PPA_SRM_COLOR_MODE_YUV420:
case PPA_SRM_COLOR_MODE_YUV444: // YUV444 not supported by PPA hardware, but can be converted by 2D-DMA before/after PPA
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_SRM_COLOR_MODE_YUV422:
case PPA_SRM_COLOR_MODE_GRAY8:
#endif
return true;
default:
return false;
}
}
/**
* @brief Set the source image color mode for PPA Scaling-Rotating-Mirroring engine RX
*
@@ -191,6 +245,14 @@ static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo
case PPA_SRM_COLOR_MODE_YUV420:
val = 8;
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_SRM_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_SRM_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported SRM rx color mode
abort();
@@ -220,6 +282,14 @@ static inline void ppa_ll_srm_set_tx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo
case PPA_SRM_COLOR_MODE_YUV420:
val = 8;
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_SRM_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_SRM_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported SRM tx color mode
abort();
@@ -311,6 +381,38 @@ static inline void ppa_ll_srm_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t
}
}
/**
* @brief Set PPA SRM input side YUV422 data format packing order
*
* @param dev Peripheral instance address
* @param pack_order One of the pack order options in color_yuv422_pack_order_t
*/
static inline void ppa_ll_srm_set_rx_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (pack_order) {
case COLOR_YUV422_PACK_ORDER_YVYU:
dev->sr_color_mode.yuv422_rx_byte_order = 0;
break;
case COLOR_YUV422_PACK_ORDER_YUYV:
dev->sr_color_mode.yuv422_rx_byte_order = 1;
break;
case COLOR_YUV422_PACK_ORDER_VYUY:
dev->sr_color_mode.yuv422_rx_byte_order = 2;
break;
case COLOR_YUV422_PACK_ORDER_UYVY:
dev->sr_color_mode.yuv422_rx_byte_order = 3;
break;
default:
// Unsupported YUV422 pack order
abort();
}
#else
// YUV422 not supported by PPA SRM hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Enable PPA SRM input data swap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR)
*
@@ -371,6 +473,112 @@ static inline void ppa_ll_srm_configure_rx_alpha(ppa_dev_t *dev, ppa_alpha_updat
}
}
/**
* @brief Get the current configured PPA SRM macro block size
*
* @param dev Peripheral instance address
* @return The current configured macro block size, one of the values in ppa_ll_srm_mb_size_t
*/
static inline ppa_ll_srm_mb_size_t ppa_ll_srm_get_mb_size(ppa_dev_t *dev)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
return (dev->sr_byte_order.sr_bk_size_sel == 0) ? PPA_LL_SRM_MB_SIZE_32_32 : PPA_LL_SRM_MB_SIZE_16_16;
#else
return PPA_LL_SRM_MB_SIZE_16_16;
#endif
}
/**
* @brief Set PPA SRM macro block size
*
* @param dev Peripheral instance address
* @param mb_size Macro block size to be set, one of the values in ppa_ll_srm_mb_size_t
*/
static inline void ppa_ll_srm_set_mb_size(ppa_dev_t *dev, ppa_ll_srm_mb_size_t mb_size)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (mb_size) {
case PPA_LL_SRM_MB_SIZE_16_16:
dev->sr_byte_order.sr_bk_size_sel = 1;
break;
case PPA_LL_SRM_MB_SIZE_32_32:
dev->sr_byte_order.sr_bk_size_sel = 0;
break;
default:
// Unsupported SRM macro block size
abort();
}
#else
HAL_ASSERT(mb_size == PPA_LL_SRM_MB_SIZE_16_16);
#endif
}
/**
* @brief Retrieve the 2D-DMA descriptor port mode block size (in pixel) according to the PPA SRM input color mode and configured macro block size
*
* @param dev Peripheral instance address
* @param in_color_mode Input color mode, one of the values in ppa_srm_color_mode_t
* @param mb_size SRM macro block size, one of the values in ppa_ll_srm_mb_size_t
* @param[out] block_h Returned block horizontal width
* @param[out] block_v Returned block wvertical height
*/
static inline void ppa_ll_srm_get_dma_dscr_port_mode_block_size(ppa_dev_t *dev, ppa_srm_color_mode_t in_color_mode, ppa_ll_srm_mb_size_t mb_size, uint32_t *block_h, uint32_t *block_v)
{
if (mb_size == PPA_LL_SRM_MB_SIZE_16_16) {
switch (in_color_mode) {
case PPA_SRM_COLOR_MODE_ARGB8888:
case PPA_SRM_COLOR_MODE_RGB888:
case PPA_SRM_COLOR_MODE_RGB565:
case PPA_SRM_COLOR_MODE_GRAY8:
*block_h = 18;
*block_v = 18;
break;
case PPA_SRM_COLOR_MODE_YUV420:
*block_h = 20;
*block_v = 18;
break;
case PPA_SRM_COLOR_MODE_YUV422:
*block_h = 20;
*block_v = 20;
break;
default:
// Unsupported SRM input color mode
*block_h = 0;
*block_v = 0;
}
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
else if (mb_size == PPA_LL_SRM_MB_SIZE_32_32) {
switch (in_color_mode) {
case PPA_SRM_COLOR_MODE_ARGB8888:
case PPA_SRM_COLOR_MODE_RGB888:
case PPA_SRM_COLOR_MODE_RGB565:
case PPA_SRM_COLOR_MODE_GRAY8:
*block_h = 34;
*block_v = 34;
break;
case PPA_SRM_COLOR_MODE_YUV420:
*block_h = 36;
*block_v = 34;
break;
case PPA_SRM_COLOR_MODE_YUV422:
*block_h = 36;
*block_v = 36;
break;
default:
// Unsupported SRM input color mode
*block_h = 0;
*block_v = 0;
}
}
#endif
else {
// Unsupported SRM macro block size
*block_h = 0;
*block_v = 0;
}
}
//////////////////////////////////// Blending ////////////////////////////////////////
/*
* Alpha Blending Calculation:
@@ -420,6 +628,33 @@ static inline void ppa_ll_blend_start(ppa_dev_t *dev, ppa_ll_blend_trans_mode_t
dev->blend_trans_mode.blend_trans_mode_update = 1;
}
/**
* @brief Check if the given color mode is supported by PPA blending engine
*
* @param color_mode One of the values in ppa_blend_color_mode_t
* @return true if supported (by any of rx_bg, rx_fg, tx); false if not supported
*/
static inline bool ppa_ll_blend_is_color_mode_supported(ppa_blend_color_mode_t color_mode)
{
switch (color_mode) {
case PPA_BLEND_COLOR_MODE_ARGB8888:
case PPA_BLEND_COLOR_MODE_RGB888:
case PPA_BLEND_COLOR_MODE_RGB565:
case PPA_BLEND_COLOR_MODE_A8:
case PPA_BLEND_COLOR_MODE_A4:
// case PPA_BLEND_COLOR_MODE_L8:
// case PPA_BLEND_COLOR_MODE_L4:
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_BLEND_COLOR_MODE_YUV420:
case PPA_BLEND_COLOR_MODE_YUV422:
case PPA_BLEND_COLOR_MODE_GRAY8:
#endif
return true;
default:
return false;
}
}
/**
* @brief Set the source image color mode for background for PPA blending engine RX
*
@@ -445,6 +680,17 @@ static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_c
// case PPA_BLEND_COLOR_MODE_L4:
// val = 5;
// break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_BLEND_COLOR_MODE_YUV420:
val = 8;
break;
case PPA_BLEND_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_BLEND_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported blending rx background color mode
abort();
@@ -509,6 +755,17 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo
case PPA_BLEND_COLOR_MODE_RGB565:
val = 2;
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_BLEND_COLOR_MODE_YUV420:
val = 8;
break;
case PPA_BLEND_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_BLEND_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported blending tx color mode
abort();
@@ -516,6 +773,142 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo
dev->blend_color_mode.blend_tx_cm = val;
}
/**
* @brief Set YUV to RGB protocol when PPA blending source image background pixel color space is YUV
*
* @param dev Peripheral instance address
* @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t
*/
static inline void ppa_ll_blend_set_rx_bg_yuv2rgb_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (std) {
case PPA_COLOR_CONV_STD_RGB_YUV_BT601:
dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 0;
break;
case PPA_COLOR_CONV_STD_RGB_YUV_BT709:
dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 1;
break;
default:
// Unsupported RGB-YUV conversion standard
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set RGB to YUV protocol when PPA blending destination image pixel color space is YUV
*
* @param dev Peripheral instance address
* @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t
*/
static inline void ppa_ll_blend_set_tx_rgb2yuv_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (std) {
case PPA_COLOR_CONV_STD_RGB_YUV_BT601:
dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 0;
break;
case PPA_COLOR_CONV_STD_RGB_YUV_BT709:
dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 1;
break;
default:
// Unsupported RGB-YUV conversion standard
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set PPA blending source image background YUV input range
*
* @param dev Peripheral instance address
* @param range One of color range options in ppa_color_range_t
*/
static inline void ppa_ll_blend_set_rx_bg_yuv_range(ppa_dev_t *dev, ppa_color_range_t range)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (range) {
case PPA_COLOR_RANGE_LIMIT:
dev->blend_color_mode.blend0_rx_yuv_range = 0;
break;
case PPA_COLOR_RANGE_FULL:
dev->blend_color_mode.blend0_rx_yuv_range = 1;
break;
default:
// Unsupported color range
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set PPA blending destination image YUV output range
*
* @param dev Peripheral instance address
* @param range One of color range options in ppa_color_range_t
*/
static inline void ppa_ll_blend_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t range)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (range) {
case PPA_COLOR_RANGE_LIMIT:
dev->blend_color_mode.blend_tx_yuv_range = 0;
break;
case PPA_COLOR_RANGE_FULL:
dev->blend_color_mode.blend_tx_yuv_range = 1;
break;
default:
// Unsupported color range
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set PPA blending source image background YUV422 data format packing order
*
* @param dev Peripheral instance address
* @param pack_order One of the pack order options in color_yuv422_pack_order_t
*/
static inline void ppa_ll_blend_set_rx_bg_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (pack_order) {
case COLOR_YUV422_PACK_ORDER_YVYU:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 0;
break;
case COLOR_YUV422_PACK_ORDER_YUYV:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 1;
break;
case COLOR_YUV422_PACK_ORDER_VYUY:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 2;
break;
case COLOR_YUV422_PACK_ORDER_UYVY:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 3;
break;
default:
// Unsupported YUV422 pack order
abort();
}
#else
// YUV422 not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Enable PPA blending input background data wrap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR)
*
@@ -639,15 +1032,44 @@ static inline void ppa_ll_blend_configure_rx_fg_alpha(ppa_dev_t *dev, ppa_alpha_
/**
* @brief Configure PPA blending pixel filling image block
*
* The color to be filled is directly relying on the blend_tx_fix_pixel register field value.
* For fill operation, the data does not go through any color space conversion in the blending engine.
*
* @param dev Peripheral instance address
* @param data The fix data to be filled to the image block pixels in ARGB8888 format
* @param color_mode One of the values in ppa_fill_color_mode_t
* @param data The point of the fix data to be filled to the image block pixels
* @param hb The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel.
* @param vb The vertical height of image block that would be filled in fix pixel filling mode. The unit is pixel.
*/
static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, color_pixel_argb8888_data_t *data, uint32_t hb, uint32_t vb)
static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, ppa_fill_color_mode_t color_mode, void *data, uint32_t hb, uint32_t vb)
{
HAL_ASSERT(hb <= PPA_BLEND_HB_V && vb <= PPA_BLEND_VB_V);
dev->blend_fix_pixel.blend_tx_fix_pixel = data->val;
uint32_t fill_color_data = 0;
switch (color_mode) {
case PPA_FILL_COLOR_MODE_ARGB8888:
case PPA_FILL_COLOR_MODE_RGB888:
case PPA_FILL_COLOR_MODE_RGB565:
case PPA_FILL_COLOR_MODE_GRAY8:
fill_color_data = *(uint32_t *)data;
break;
case PPA_FILL_COLOR_MODE_YUV422: {
color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data;
fill_color_data = ((yuv_data->y) << 24) | ((yuv_data->v) << 16) | ((yuv_data->y) << 8) | (yuv_data->u);
break;
}
// case PPA_FILL_COLOR_MODE_YUV420: {
// color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data;
// if (yuv_data->u != yuv_data->v) {
// abort();
// }
// fill_color_data = ((yuv_data->y) << 16) | ((yuv_data->y) << 8) | (yuv_data->v);
// break;
// }
default:
// Unsupported filling color mode
abort();
}
dev->blend_fix_pixel.blend_tx_fix_pixel = fill_color_data;
dev->blend_tx_size.blend_hb = hb;
dev->blend_tx_size.blend_vb = vb;
}
components/hal/esp32p4/include/hal/uart_ll.h
+1 -1
View File
@@ -660,7 +660,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{
for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte;
buf[i] = hw->fifo.val;
}
}