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feat(gdma): add burst size validation check during config

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Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Chen Chen
2026-09-01 16:07:51 +08:00
co-authored by Cursor
parent dce5812654
commit 1dfce4409a
18 changed files with 154 additions and 16 deletions
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components/esp_hal_dma/esp32c5/include/hal/ahb_dma_ll.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,6 +21,11 @@ extern "C" {
#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
#define AHB_DMA_LL_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_4 | \
GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32 | \
GDMA_BURST_SIZE_SUPPORT_64)
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_CHANNEL_MAX_WEIGHT 15 // supported weight levels: [0,15]
components/esp_hal_dma/esp32c61/include/hal/ahb_dma_ll.h
+4
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@@ -21,6 +21,10 @@ extern "C" {
#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
#define AHB_DMA_LL_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_4 | \
GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32)
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_CHANNEL_MAX_WEIGHT 15 // supported weight levels: [0,15]
components/esp_hal_dma/esp32h4/include/hal/ahb_dma_ll.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,6 +21,11 @@ extern "C" {
#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
#define AHB_DMA_LL_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_4 | \
GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32 | \
GDMA_BURST_SIZE_SUPPORT_64)
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define AHB_DMA_LL_RX_EVENT_MASK (0x7F)
components/esp_hal_dma/esp32p4/include/hal/ahb_dma_ll.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,6 +22,11 @@ extern "C" {
#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : NULL)
#define AHB_DMA_LL_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_4 | \
GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32 | \
GDMA_BURST_SIZE_SUPPORT_64)
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFAC2)
#define AHB_DMA_LL_RX_EVENT_MASK (0x1F)
components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h
+6
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@@ -24,6 +24,12 @@ extern "C" {
#define AXI_DMA_LL_GET_HW(id) (((id) == 0) ? (&AXI_DMA) : NULL)
#define AXI_DMA_LL_SUPPORT(_feat) AXI_DMA_LL_SUPPORT_ ## _feat
#define AXI_DMA_LL_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_8 | \
GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32 | \
GDMA_BURST_SIZE_SUPPORT_64 | \
GDMA_BURST_SIZE_SUPPORT_128)
// any "dummy" peripheral ID can be used for M2M mode
#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
#define AXI_DMA_LL_RX_EVENT_MASK (0x1F)
components/esp_hal_dma/esp32s3/include/hal/gdma_ll.h
+4
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@@ -19,6 +19,10 @@
#define GDMA_LL_INST_NUM 1
#define GDMA_LL_PAIRS_PER_INST GDMA_LL_AHB_PAIRS_PER_GROUP
#define GDMA_LL_AHB_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32 | \
GDMA_BURST_SIZE_SUPPORT_64)
#ifdef __cplusplus
extern "C" {
#endif
components/esp_hal_dma/esp32s31/include/hal/ahb_dma_ll.h
+5
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@@ -20,6 +20,11 @@ extern "C" {
#define AHB_DMA_LL_GET_HW(id) (((id) == 0) ? (&AHB_DMA) : (((id) == 2) ? ((ahb_dma_dev_t *)&LP_AHB_DMA) : NULL))
#define AHB_DMA_LL_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_4 | \
GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32 | \
GDMA_BURST_SIZE_SUPPORT_64)
// any "dummy" peripheral ID can be used for M2M mode
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0x8200)
#define AHB_DMA_LL_RX_EVENT_MASK (0x7F)
components/esp_hal_dma/esp32s31/include/hal/axi_dma_ll.h
+6
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@@ -23,6 +23,12 @@ extern "C" {
#define AXI_DMA_LL_GET_HW(id) (((id) == 0) ? (&AXI_DMA) : NULL)
#define AXI_DMA_LL_SUPPORT(_feat) AXI_DMA_LL_SUPPORT_ ## _feat
#define AXI_DMA_LL_SUPPORTED_BURST_SIZE_MASK (GDMA_BURST_SIZE_SUPPORT_8 | \
GDMA_BURST_SIZE_SUPPORT_16 | \
GDMA_BURST_SIZE_SUPPORT_32 | \
GDMA_BURST_SIZE_SUPPORT_64 | \
GDMA_BURST_SIZE_SUPPORT_128)
// any "dummy" peripheral ID can be used for M2M mode
#define AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFFC0)
#define AXI_DMA_LL_RX_EVENT_MASK (0x7F)
components/esp_hal_dma/gdma_hal_ahb_v1.c
+3
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@@ -13,6 +13,9 @@ static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
.m2m_free_periph_mask = GDMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = GDMA_LL_TX_EVENT_MASK,
.rx_event_mask = GDMA_LL_RX_EVENT_MASK,
#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
.supported_burst_size_mask = GDMA_LL_AHB_SUPPORTED_BURST_SIZE_MASK,
#endif
};
void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
components/esp_hal_dma/gdma_hal_ahb_v2.c
+6
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@@ -14,6 +14,9 @@ static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
.m2m_free_periph_mask = AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = AHB_DMA_LL_TX_EVENT_MASK,
.rx_event_mask = AHB_DMA_LL_RX_EVENT_MASK,
#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
.supported_burst_size_mask = AHB_DMA_LL_SUPPORTED_BURST_SIZE_MASK,
#endif
};
void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
@@ -315,6 +318,9 @@ static gdma_hal_priv_data_t gdma_lp_ahb_hal_priv_data = {
.m2m_free_periph_mask = LP_AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = AHB_DMA_LL_TX_EVENT_MASK,
.rx_event_mask = AHB_DMA_LL_RX_EVENT_MASK,
#if GDMA_LL_GET(AHB_BURST_SIZE_ADJUSTABLE)
.supported_burst_size_mask = AHB_DMA_LL_SUPPORTED_BURST_SIZE_MASK,
#endif
};
void gdma_lp_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
components/esp_hal_dma/gdma_hal_axi.c
+1
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@@ -14,6 +14,7 @@ static gdma_hal_priv_data_t gdma_axi_hal_priv_data = {
.m2m_free_periph_mask = AXI_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
.tx_event_mask = AXI_DMA_LL_TX_EVENT_MASK,
.rx_event_mask = AXI_DMA_LL_RX_EVENT_MASK,
.supported_burst_size_mask = AXI_DMA_LL_SUPPORTED_BURST_SIZE_MASK,
};
void gdma_axi_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
components/esp_hal_dma/gdma_hal_top.c
+13
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@@ -65,6 +65,19 @@ void gdma_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_
}
}
bool gdma_hal_check_burst_size(gdma_hal_context_t *hal, uint32_t burst_sz)
{
if (burst_sz & (burst_sz - 1)) {
// Not a power of 2
return false;
}
if (!hal->set_burst_size) {
// When a specific burst size cannot be set (using fixed burst size)
return true;
}
return (hal->priv_data->supported_burst_size_mask & burst_sz) != 0;
}
void gdma_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back, bool eof_till_popped)
{
hal->set_strategy(hal, chan_id, dir, en_owner_check, en_desc_write_back, eof_till_popped);
components/esp_hal_dma/include/hal/gdma_hal.h
+4
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@@ -55,6 +55,8 @@ typedef struct {
// Supported interrupt events can vary across DMA instances (e.g. AHB vs AXI)
uint32_t tx_event_mask;
uint32_t rx_event_mask;
// Bitmap of supported configurable data burst sizes, using gdma_burst_size_support_t
uint32_t supported_burst_size_mask;
} gdma_hal_priv_data_t;
/**
@@ -128,6 +130,8 @@ void gdma_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_di
void gdma_hal_set_burst_size(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t burst_sz);
bool gdma_hal_check_burst_size(gdma_hal_context_t *hal, uint32_t burst_sz);
void gdma_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back, bool eof_till_popped);
void gdma_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis);
components/esp_hal_dma/include/hal/gdma_types.h
+13 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,6 +22,18 @@ typedef enum {
GDMA_CHANNEL_DIRECTION_RX, /*!< GDMA channel direction: RX */
} gdma_channel_direction_t;
/**
* @brief Bit definitions used by the LL layer to describe supported data burst sizes
*/
typedef enum {
GDMA_BURST_SIZE_SUPPORT_4 = 1U << 2,
GDMA_BURST_SIZE_SUPPORT_8 = 1U << 3,
GDMA_BURST_SIZE_SUPPORT_16 = 1U << 4,
GDMA_BURST_SIZE_SUPPORT_32 = 1U << 5,
GDMA_BURST_SIZE_SUPPORT_64 = 1U << 6,
GDMA_BURST_SIZE_SUPPORT_128 = 1U << 7,
} gdma_burst_size_support_t;
/**
* @brief GDMA channel events that supported by the ETM module
*/