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Merge branch 'feat/uhci_esp32s31_support' into 'master'

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feat(uhci): Add support for uhci on esp32s31

Closes IDF-14791

See merge request espressif/esp-idf!47730
This commit is contained in:
morris
2026-04-21 15:57:55 +08:00
parent 96194f19a6 131bb462a4
commit 1dcd6fcf08
10 changed files with 254 additions and 192 deletions
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components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -15,6 +15,10 @@ config SOC_GDMA_SUPPORTED
bool
default y
config SOC_UHCI_SUPPORTED
bool
default y
config SOC_AHB_GDMA_SUPPORTED
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+1 -1
View File
@@ -28,7 +28,7 @@
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
// #define SOC_UHCI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14791
#define SOC_UHCI_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_AXI_GDMA_SUPPORTED 1
#define SOC_LP_AHB_GDMA_SUPPORTED 1
components/soc/esp32s31/register/soc/uhci_struct.h
+19 -184
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -315,187 +315,31 @@ typedef union {
uint32_t val;
} uhci_quick_sent_reg_t;
/** Type of reg_q0_word0 register
* Q0 WORD0 quick send register
/** Type of reg_qn_word0 register
* a
*/
typedef union {
struct {
/** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q0 register.
/** send_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q0_word0:32;
uint32_t send_word0:32;
};
uint32_t val;
} uhci_reg_q0_word0_reg_t;
} uhci_reg_qn_word0_reg_t;
/** Type of reg_q0_word1 register
* Q0 WORD1 quick send register
/** Type of reg_qn_word1 register
* a
*/
typedef union {
struct {
/** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q0 register.
/** send_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q0_word1:32;
uint32_t send_word1:32;
};
uint32_t val;
} uhci_reg_q0_word1_reg_t;
/** Type of reg_q1_word0 register
* Q1 WORD0 quick send register
*/
typedef union {
struct {
/** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q1 register.
*/
uint32_t send_q1_word0:32;
};
uint32_t val;
} uhci_reg_q1_word0_reg_t;
/** Type of reg_q1_word1 register
* Q1 WORD1 quick send register
*/
typedef union {
struct {
/** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q1 register.
*/
uint32_t send_q1_word1:32;
};
uint32_t val;
} uhci_reg_q1_word1_reg_t;
/** Type of reg_q2_word0 register
* Q2 WORD0 quick send register
*/
typedef union {
struct {
/** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q2 register.
*/
uint32_t send_q2_word0:32;
};
uint32_t val;
} uhci_reg_q2_word0_reg_t;
/** Type of reg_q2_word1 register
* Q2 WORD1 quick send register
*/
typedef union {
struct {
/** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q2 register.
*/
uint32_t send_q2_word1:32;
};
uint32_t val;
} uhci_reg_q2_word1_reg_t;
/** Type of reg_q3_word0 register
* Q3 WORD0 quick send register
*/
typedef union {
struct {
/** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q3 register.
*/
uint32_t send_q3_word0:32;
};
uint32_t val;
} uhci_reg_q3_word0_reg_t;
/** Type of reg_q3_word1 register
* Q3 WORD1 quick send register
*/
typedef union {
struct {
/** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q3 register.
*/
uint32_t send_q3_word1:32;
};
uint32_t val;
} uhci_reg_q3_word1_reg_t;
/** Type of reg_q4_word0 register
* Q4 WORD0 quick send register
*/
typedef union {
struct {
/** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q4 register.
*/
uint32_t send_q4_word0:32;
};
uint32_t val;
} uhci_reg_q4_word0_reg_t;
/** Type of reg_q4_word1 register
* Q4 WORD1 quick send register
*/
typedef union {
struct {
/** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q4 register.
*/
uint32_t send_q4_word1:32;
};
uint32_t val;
} uhci_reg_q4_word1_reg_t;
/** Type of reg_q5_word0 register
* Q5 WORD0 quick send register
*/
typedef union {
struct {
/** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q5 register.
*/
uint32_t send_q5_word0:32;
};
uint32_t val;
} uhci_reg_q5_word0_reg_t;
/** Type of reg_q5_word1 register
* Q5 WORD1 quick send register
*/
typedef union {
struct {
/** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q5 register.
*/
uint32_t send_q5_word1:32;
};
uint32_t val;
} uhci_reg_q5_word1_reg_t;
/** Type of reg_q6_word0 register
* Q6 WORD0 quick send register
*/
typedef union {
struct {
/** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q6 register.
*/
uint32_t send_q6_word0:32;
};
uint32_t val;
} uhci_reg_q6_word0_reg_t;
/** Type of reg_q6_word1 register
* Q6 WORD1 quick register
*/
typedef union {
struct {
/** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
* Data to be transmitted in Q6 register.
*/
uint32_t send_q6_word1:32;
};
uint32_t val;
} uhci_reg_q6_word1_reg_t;
} uhci_reg_qn_word1_reg_t;
/** Type of esc_conf0 register
* Escape sequence configuration register 0
@@ -861,7 +705,7 @@ typedef union {
} uhci_date_reg_t;
typedef struct {
typedef struct uhci_dev_t {
volatile uhci_conf0_reg_t conf0;
volatile uhci_int_raw_reg_t int_raw;
volatile uhci_int_st_reg_t int_st;
@@ -875,20 +719,10 @@ typedef struct {
volatile uhci_ack_num_reg_t ack_num;
volatile uhci_rx_head_reg_t rx_head;
volatile uhci_quick_sent_reg_t quick_sent;
volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
volatile struct {
uhci_reg_qn_word0_reg_t word0;
uhci_reg_qn_word1_reg_t word1;
} q_data[7];
volatile uhci_esc_conf0_reg_t esc_conf0;
volatile uhci_esc_conf1_reg_t esc_conf1;
volatile uhci_esc_conf2_reg_t esc_conf2;
@@ -897,6 +731,7 @@ typedef struct {
volatile uhci_date_reg_t date;
} uhci_dev_t;
extern uhci_dev_t UHCI0;
#ifndef __cplusplus
_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");