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Merge branch 'feat/support_gpio_source_for_more_chips' into 'master'

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feat(esp_hw_support): support GPIO wakeup deepsleep on esp32/esp32s2/esp32s3

Closes PM-666

See merge request espressif/esp-idf!45773
This commit is contained in:
Wu Zheng Hui
2026-03-26 11:28:45 +08:00
parent ae463064d7 61dc18139a
commit 1dbf5247d1
38 changed files with 299 additions and 132 deletions
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components/soc/esp32/include/soc/Kconfig.soc_caps.in
+8
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@@ -343,6 +343,14 @@ config SOC_GPIO_PIN_COUNT
int
default 40
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0xFFFFFFFFFF
components/soc/esp32/include/soc/soc_caps.h
+4
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@@ -183,6 +183,10 @@
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT 40
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT2 | BIT4 | BIT12 | BIT13 | BIT14 | BIT15 | BIT25 | BIT26 | BIT27 | BIT32 | BIT33 | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39)
// 0~39 valid except 24, 28~31
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// GPIO >= 34 are input only
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
-4
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@@ -315,10 +315,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 6
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00000000001FFFC0
components/soc/esp32c2/include/soc/soc_caps.h
-1
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@@ -142,7 +142,6 @@
#define SOC_GPIO_OUT_RANGE_MAX 20
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
-4
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@@ -411,10 +411,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 6
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00000000003FFFC0
components/soc/esp32c3/include/soc/soc_caps.h
-1
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@@ -181,7 +181,6 @@
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-4
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@@ -591,10 +591,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 7
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0000000001FFFF80
components/soc/esp32c5/include/soc/soc_caps.h
-1
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@@ -236,7 +236,6 @@
#define SOC_GPIO_OUT_RANGE_MAX 28
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-4
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@@ -507,10 +507,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 8
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000007FFFFF00
components/soc/esp32c6/include/soc/soc_caps.h
-1
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@@ -209,7 +209,6 @@
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (8)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
-4
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@@ -463,10 +463,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 7
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x3FFFFF80
components/soc/esp32c61/include/soc/soc_caps.h
-1
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@@ -192,7 +192,6 @@
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
-4
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@@ -415,10 +415,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 6
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
-1
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@@ -227,7 +227,6 @@
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1))
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-4
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@@ -715,10 +715,6 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 16
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x007FFFFFFFFF0000
components/soc/esp32p4/include/soc/soc_caps.h
-1
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@@ -270,7 +270,6 @@
#define SOC_GPIO_OUT_RANGE_MAX 54
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | 0xFFFF)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (16)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+8
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@@ -435,6 +435,14 @@ config SOC_RTC_CNTL_NEEDS_ATOMIC_ACCESS
bool
default y
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_DEDIC_GPIO_HAS_INTERRUPT
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
+5
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@@ -204,6 +204,11 @@
* (e.g., spinlocks) when accessed from multiple cores or threads. */
#define SOC_RTC_CNTL_NEEDS_ATOMIC_ACCESS 1
// GPIO0~21 on ESP32-S2 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14 | BIT15 | BIT16 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21)
/*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
#define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+8
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@@ -483,6 +483,14 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_I2C_NUM
int
default 2
components/soc/esp32s3/include/soc/soc_caps.h
+5
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@@ -201,6 +201,11 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// GPIO0~21 on ESP32-S3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14 | BIT15 | BIT16 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21)
/*-------------------------- I2C CAPS ----------------------------------------*/
#define SOC_I2C_NUM (2U)
#define SOC_HP_I2C_NUM (2U)