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Break out high-level interrupts so a component can override them
This commit is contained in:
Jeroen Domburg
@@ -0,0 +1,158 @@
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "xtensa_rtos.h"
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#include "esp_panic.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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/*
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This file contains the default handlers for the high interrupt levels as well as some specialized exceptions.
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The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
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*/
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#if XCHAL_HAVE_DEBUG
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.global xt_debugexception
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.weak xt_debugexception
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.set xt_debugexception, _xt_debugexception
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.section .iram1,"ax"
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.type _xt_debugexception,@function
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.align 4
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_xt_debugexception:
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movi a0,PANIC_RSN_DEBUGEXCEPTION
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wsr a0,EXCCAUSE
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call0 _xt_panic /* does not return */
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rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL
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rfi XCHAL_DEBUGLEVEL
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#endif /* Debug exception */
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#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
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.global xt_highint2
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.weak xt_highint2
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.set xt_highint2, _xt_highint2
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.section .iram1,"ax"
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.type _xt_highint2,@function
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.align 4
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_xt_highint2:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint2_exit:
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rsr a0, EXCSAVE_2 /* restore a0 */
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rfi 2
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#endif /* Level 2 */
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#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
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.global xt_highint3
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.weak xt_highint3
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.set xt_highint3, _xt_highint3
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.section .iram1,"ax"
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.type _xt_highint3,@function
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.align 4
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_xt_highint3:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint3_exit:
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rsr a0, EXCSAVE_3 /* restore a0 */
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rfi 3
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#endif /* Level 3 */
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#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
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.global xt_highint4
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.weak xt_highint4
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.set xt_highint4, _xt_highint4
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.section .iram1,"ax"
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.type _xt_highint4,@function
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.align 4
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_xt_highint4:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint4_exit:
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rsr a0, EXCSAVE_4 /* restore a0 */
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rfi 4
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#endif /* Level 4 */
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#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
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.global xt_highint5
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.weak xt_highint5
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.set xt_highint5, _xt_highint5
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.section .iram1,"ax"
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.type _xt_highint5,@function
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.align 4
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_xt_highint5:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint5_exit:
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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#endif /* Level 5 */
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#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
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.global _xt_highint6
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.global xt_highint6
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.weak xt_highint6
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.set xt_highint6, _xt_highint6
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.section .iram1,"ax"
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.type _xt_highint6,@function
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.align 4
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_xt_highint6:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint6_exit:
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rsr a0, EXCSAVE_6 /* restore a0 */
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rfi 6
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#endif /* Level 6 */
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#if XCHAL_HAVE_NMI
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.global _xt_nmi
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.global xt_nmi
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.weak xt_nmi
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.set xt_nmi, _xt_nmi
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.section .iram1,"ax"
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.type _xt_nmi,@function
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.align 4
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_xt_nmi:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_nmi_exit:
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rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */
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rfi XCHAL_NMILEVEL
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#endif /* NMI */
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@@ -471,28 +471,10 @@ Debug Exception.
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.section .DebugExceptionVector.text, "ax"
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.global _DebugExceptionVector
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.align 4
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.global xt_debugexception
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_DebugExceptionVector:
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#ifdef XT_SIMULATOR
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/*
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In the simulator, let the debugger (if any) handle the debug exception,
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or simply stop the simulation:
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*/
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wsr a2, EXCSAVE+XCHAL_DEBUGLEVEL /* save a2 where sim expects it */
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movi a2, SYS_gdb_enter_sktloop
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simcall /* have ISS handle debug exc. */
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#elif 0 /* change condition to 1 to use the HAL minimal debug handler */
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wsr a3, EXCSAVE+XCHAL_DEBUGLEVEL
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movi a3, xthal_debugexc_defhndlr_nw /* use default debug handler */
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jx a3
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#else
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wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* save original a0 somewhere */
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movi a0,PANIC_RSN_DEBUGEXCEPTION
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wsr a0,EXCCAUSE
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call0 _xt_panic /* does not return */
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rfi XCHAL_DEBUGLEVEL /* make a0 point here not later */
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#endif
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wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* preserve a0 */
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call0 xt_debugexception /* load exception handler */
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.end literal_prefix
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@@ -1060,9 +1042,6 @@ locking.
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/* Co-processor exception occurred outside a thread (not supported). */
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.L_xt_coproc_invalid:
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#if XCHAL_HAVE_DEBUG
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break 1, 1 /* unhandled user exception */
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#endif
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movi a0,PANIC_RSN_COPROCEXCEPTION
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wsr a0,EXCCAUSE
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call0 _xt_panic /* not in a thread (invalid) */
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@@ -1531,9 +1510,9 @@ the minimum necessary before jumping to the handler in the .text section.
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*******************************************************************************/
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/*
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Currently only shells for high priority interrupt handlers are provided
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here. However a template and example can be found in the Cadence Design Systems tools
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documentation: "Microprocessor Programmer's Guide".
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These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define
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these in an external assembly source file. If these symbols are not defined anywhere
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else, the defaults in xtensa_vector_defaults.S are used.
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*/
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#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
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@@ -1542,37 +1521,14 @@ documentation: "Microprocessor Programmer's Guide".
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.section .Level2InterruptVector.text, "ax"
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.global _Level2Vector
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.type _Level2Vector,@function
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.global xt_highint2
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.align 4
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_Level2Vector:
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wsr a0, EXCSAVE_2 /* preserve a0 */
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call0 _xt_highint2 /* load interrupt handler */
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call0 xt_highint2 /* load interrupt handler */
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.end literal_prefix
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.section .iram1,"ax"
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.type _xt_highint2,@function
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.align 4
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_xt_highint2:
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#ifdef XT_INTEXC_HOOKS
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/* Call interrupt hook if present to (pre)handle interrupts. */
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 2<<2
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beqz a0, 1f
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.Ln_xt_highint2_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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1:
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#endif
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/* USER_EDIT:
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ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
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*/
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.align 4
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.L_xt_highint2_exit:
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rsr a0, EXCSAVE_2 /* restore a0 */
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rfi 2
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#endif /* Level 2 */
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#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
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@@ -1581,38 +1537,15 @@ _xt_highint2:
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.section .Level3InterruptVector.text, "ax"
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.global _Level3Vector
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.type _Level3Vector,@function
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.global xt_highint3
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.align 4
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_Level3Vector:
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wsr a0, EXCSAVE_3 /* preserve a0 */
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call0 _xt_highint3 /* load interrupt handler */
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call0 xt_highint3 /* load interrupt handler */
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/* never returns here - call0 is used as a jump (see note at top) */
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.end literal_prefix
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.section .iram1,"ax"
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.type _xt_highint3,@function
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.align 4
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_xt_highint3:
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#ifdef XT_INTEXC_HOOKS
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/* Call interrupt hook if present to (pre)handle interrupts. */
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 3<<2
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beqz a0, 1f
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.Ln_xt_highint3_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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1:
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#endif
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/* USER_EDIT:
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ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
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*/
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.align 4
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.L_xt_highint3_exit:
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rsr a0, EXCSAVE_3 /* restore a0 */
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rfi 3
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#endif /* Level 3 */
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#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
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@@ -1621,110 +1554,15 @@ _xt_highint3:
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.section .Level4InterruptVector.text, "ax"
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.global _Level4Vector
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.type _Level4Vector,@function
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.global xt_highint4
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.align 4
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_Level4Vector:
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wsr a0, EXCSAVE_4 /* preserve a0 */
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call0 _xt_highint4 /* load interrupt handler */
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call0 xt_highint4 /* load interrupt handler */
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/* never returns here - call0 is used as a jump (see note at top) */
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.end literal_prefix
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.section .iram1,"ax"
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.type _xt_highint4,@function
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.align 4
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_xt_highint4:
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#ifdef XT_INTEXC_HOOKS
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/* Call interrupt hook if present to (pre)handle interrupts. */
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 4<<2
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beqz a0, 1f
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.Ln_xt_highint4_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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1:
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#endif
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/* On the ESP32, this level is used for panic events that are detected by hardware and should
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also panic when interrupts are disabled. At the moment, these are the interrupt watchdog
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as well as the cache invalid access interrupt. (24 and 25) */
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/* Allocate exception frame and save minimal context. */
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mov a0, sp
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addi sp, sp, -XT_STK_FRMSZ
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s32i a0, sp, XT_STK_A1
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -12 /* for debug backtrace */
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#endif
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rsr a0, PS /* save interruptee's PS */
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s32i a0, sp, XT_STK_PS
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rsr a0, EPC_4 /* save interruptee's PC */
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s32i a0, sp, XT_STK_PC
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -16 /* for debug backtrace */
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#endif
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s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
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s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
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call0 _xt_context_save
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/* Save vaddr into exception frame */
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rsr a0, EXCVADDR
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s32i a0, sp, XT_STK_EXCVADDR
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/* Figure out reason, save into EXCCAUSE reg */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_CACHEERR_INUM, 1 /* get cacheerr int bit */
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beqz a0, 1f
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/* Kill this interrupt; we cannot reset it. */
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rsr a0, INTENABLE
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movi a4, ~(1<<ETS_CACHEERR_INUM)
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and a0, a4, a0
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wsr a0, INTENABLE
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movi a0, PANIC_RSN_CACHEERR
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j 9f
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1:
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#if CONFIG_INT_WDT_CHECK_CPU1
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/* Check if the cause is the app cpu failing to tick.*/
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movi a0, int_wdt_app_cpu_ticked
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l32i a0, a0, 0
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bnez a0, 2f
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/* It is. Modify cause. */
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movi a0,PANIC_RSN_INTWDT_CPU1
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j 9f
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2:
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#endif
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/* Set EXCCAUSE to reflect cause of the wdt int trigger */
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movi a0,PANIC_RSN_INTWDT_CPU0
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9:
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/* Found the reason, now save it. */
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s32i a0, sp, XT_STK_EXCCAUSE
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/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
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rsr a0, EXCSAVE_4 /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
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movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
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wsr a0, PS
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//Call panic handler
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mov a6,sp
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call4 panicHandler
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call0 _xt_context_restore
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l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
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wsr a0, PS
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l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
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wsr a0, EPC_4
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l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
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l32i sp, sp, XT_STK_A1 /* remove exception frame */
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rsync /* ensure PS and EPC written */
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rsr a0, EXCSAVE_4 /* restore a0 */
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rfi 4
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#endif /* Level 4 */
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#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
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@@ -1733,96 +1571,15 @@ _xt_highint4:
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.section .Level5InterruptVector.text, "ax"
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.global _Level5Vector
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.type _Level5Vector,@function
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.global xt_highint5
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.align 4
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_Level5Vector:
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wsr a0, EXCSAVE_5 /* preserve a0 */
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call0 _xt_highint5 /* load interrupt handler */
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call0 xt_highint5 /* load interrupt handler */
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/* never returns here - call0 is used as a jump (see note at top) */
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.end literal_prefix
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||||
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#define L5_INTR_STACK_SIZE 8
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#define L5_INTR_A2_OFFSET 0
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#define L5_INTR_A3_OFFSET 4
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.data
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_l5_intr_stack:
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.space L5_INTR_STACK_SIZE
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||||
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||||
.section .iram1,"ax"
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.type _xt_highint5,@function
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.align 4
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_xt_highint5:
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#ifdef XT_INTEXC_HOOKS
|
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/* Call interrupt hook if present to (pre)handle interrupts. */
|
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 5<<2
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beqz a0, 1f
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||||
.Ln_xt_highint5_call_hook:
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callx0 a0 /* must NOT disturb stack! */
|
||||
1:
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||||
#endif
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||||
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||||
/* This section is for access dport register protection */
|
||||
/* Allocate exception frame and save minimal context. */
|
||||
/* Because the interrupt cause code have protection that only
|
||||
allow one cpu enter in L5 interrupt at one time, so
|
||||
there needn't have two _l5_intr_stack for each cpu */
|
||||
|
||||
movi a0, _l5_intr_stack
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||||
s32i a2, a0, L5_INTR_A2_OFFSET
|
||||
s32i a3, a0, L5_INTR_A3_OFFSET
|
||||
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||||
/* Check interrupt */
|
||||
rsr a0, INTERRUPT
|
||||
extui a0, a0, ETS_DPORT_INUM, 1 /* get dport int bit */
|
||||
beqz a0, 1f
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||||
|
||||
/* handle dport interrupt */
|
||||
/* get CORE_ID */
|
||||
getcoreid a0
|
||||
beqz a0, 2f
|
||||
|
||||
/* current cpu is 1 */
|
||||
movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG
|
||||
movi a2, 0
|
||||
s32i a2, a0, 0 /* clear intr */
|
||||
movi a0, 0 /* other cpu id */
|
||||
j 3f
|
||||
2:
|
||||
/* current cpu is 0 */
|
||||
movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG
|
||||
movi a2, 0
|
||||
s32i a2, a0, 0 /* clear intr */
|
||||
movi a0, 1 /* other cpu id */
|
||||
3:
|
||||
/* set and wait flag */
|
||||
movi a2, dport_access_start
|
||||
addx4 a2, a0, a2
|
||||
movi a3, 1
|
||||
s32i a3, a2, 0
|
||||
memw
|
||||
movi a2, dport_access_end
|
||||
addx4 a2, a0, a2
|
||||
.check_dport_access_end:
|
||||
l32i a3, a2, 0
|
||||
beqz a3, .check_dport_access_end
|
||||
|
||||
1:
|
||||
movi a0, _l5_intr_stack
|
||||
l32i a2, a0, L5_INTR_A2_OFFSET
|
||||
l32i a3, a0, L5_INTR_A3_OFFSET
|
||||
rsync /* ensure register restored */
|
||||
|
||||
rsr a0, EXCSAVE_5 /* restore a0 */
|
||||
rfi 5
|
||||
|
||||
|
||||
.align 4
|
||||
.L_xt_highint5_exit:
|
||||
rsr a0, EXCSAVE_5 /* restore a0 */
|
||||
rfi 5
|
||||
|
||||
#endif /* Level 5 */
|
||||
|
||||
#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
|
||||
@@ -1831,38 +1588,15 @@ _xt_highint5:
|
||||
.section .Level6InterruptVector.text, "ax"
|
||||
.global _Level6Vector
|
||||
.type _Level6Vector,@function
|
||||
.global xt_highint6
|
||||
.align 4
|
||||
_Level6Vector:
|
||||
wsr a0, EXCSAVE_6 /* preserve a0 */
|
||||
call0 _xt_highint6 /* load interrupt handler */
|
||||
call0 xt_highint6 /* load interrupt handler */
|
||||
/* never returns here - call0 is used as a jump (see note at top) */
|
||||
|
||||
.end literal_prefix
|
||||
|
||||
.section .iram1,"ax"
|
||||
.type _xt_highint6,@function
|
||||
.align 4
|
||||
_xt_highint6:
|
||||
|
||||
#ifdef XT_INTEXC_HOOKS
|
||||
/* Call interrupt hook if present to (pre)handle interrupts. */
|
||||
movi a0, _xt_intexc_hooks
|
||||
l32i a0, a0, 6<<2
|
||||
beqz a0, 1f
|
||||
.Ln_xt_highint6_call_hook:
|
||||
callx0 a0 /* must NOT disturb stack! */
|
||||
1:
|
||||
#endif
|
||||
|
||||
/* USER_EDIT:
|
||||
ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
.L_xt_highint6_exit:
|
||||
rsr a0, EXCSAVE_6 /* restore a0 */
|
||||
rfi 6
|
||||
|
||||
#endif /* Level 6 */
|
||||
|
||||
#if XCHAL_HAVE_NMI
|
||||
@@ -1871,38 +1605,15 @@ _xt_highint6:
|
||||
.section .NMIExceptionVector.text, "ax"
|
||||
.global _NMIExceptionVector
|
||||
.type _NMIExceptionVector,@function
|
||||
.global xt_nmi
|
||||
.align 4
|
||||
_NMIExceptionVector:
|
||||
wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */
|
||||
call0 _xt_nmi /* load interrupt handler */
|
||||
call0 xt_nmi /* load interrupt handler */
|
||||
/* never returns here - call0 is used as a jump (see note at top) */
|
||||
|
||||
.end literal_prefix
|
||||
|
||||
.section .iram1,"ax"
|
||||
.type _xt_nmi,@function
|
||||
.align 4
|
||||
_xt_nmi:
|
||||
|
||||
#ifdef XT_INTEXC_HOOKS
|
||||
/* Call interrupt hook if present to (pre)handle interrupts. */
|
||||
movi a0, _xt_intexc_hooks
|
||||
l32i a0, a0, XCHAL_NMILEVEL<<2
|
||||
beqz a0, 1f
|
||||
.Ln_xt_nmi_call_hook:
|
||||
callx0 a0 /* must NOT disturb stack! */
|
||||
1:
|
||||
#endif
|
||||
|
||||
/* USER_EDIT:
|
||||
ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
.L_xt_nmi_exit:
|
||||
rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */
|
||||
rfi XCHAL_NMILEVEL
|
||||
|
||||
#endif /* NMI */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user