fix(pvt): fix pvt retention bug,replace pvt_retention with pvt_init

This commit is contained in:
zlq
2026-01-09 15:44:53 +08:00
parent 5a23c96295
commit 1d41de96d8
10 changed files with 29 additions and 15 deletions
+1
View File
@@ -309,6 +309,7 @@ menu "Hardware Settings"
config ESP_ENABLE_PVT
bool "Auto adjust hp & lp voltage using pvt function (MUST ENABLE FOR MP)"
depends on SOC_PMU_PVT_SUPPORTED
default n if IDF_TARGET_ESP32C6
default y
help
If enabled, hp & lp voltage can be auto adjust by PVT characteristic.
+1 -1
View File
@@ -47,7 +47,7 @@ entries:
elif PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32P4 != y:
pmu_param:get_act_hp_dbias (noflash)
pmu_param:get_act_lp_dbias (noflash)
if SOC_PMU_PVT_SUPPORTED = y:
if SOC_PMU_PVT_SUPPORTED = y && ESP_ENABLE_PVT = y:
pmu_pvt (noflash)
if PM_SLP_IRAM_OPT = y && SOC_USB_SERIAL_JTAG_SUPPORTED = y:
sleep_console (noflash)
@@ -83,7 +83,7 @@ void pvt_auto_dbias_init(void)
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
/*config for dbias func*/
CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN);
esp_rom_delay_us(100);
esp_rom_delay_us(1);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S); // Select monitor cell ,which used to monitor PVT situation
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S);
@@ -130,7 +130,6 @@ void IRAM_ATTR pvt_func_enable(bool enable)
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, pvt_lp_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias
CLEAR_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN);
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -215,6 +215,8 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
{
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
pvt_auto_dbias_init();
charge_pump_init();
pvt_func_enable(true);
charge_pump_enable(true);
#endif
@@ -353,10 +355,6 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
void rtc_clk_cpu_freq_set_xtal(void)
{
rtc_clk_cpu_set_to_default_config();
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
rtc_clk_bbpll_disable();
}
+2 -2
View File
@@ -793,7 +793,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
regi2c_tsens_reg_read();
#endif
}
#if CONFIG_ESP_ENABLE_PVT
#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
pvt_func_enable(false);
#endif
@@ -810,7 +810,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
*/
static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
{
#if CONFIG_ESP_ENABLE_PVT
#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
pvt_func_enable(true);
#endif
@@ -168,7 +168,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
err = sleep_pau_retention_init();
if(err) goto error;
#endif
#if CONFIG_ESP_ENABLE_PVT
#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_RETENTION_BY_REGDMA
err = sleep_pvt_retention_init();
if(err) goto error;
#endif