mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 11:10:54 +03:00
fix(pvt): fix pvt retention bug,replace pvt_retention with pvt_init
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@@ -309,6 +309,7 @@ menu "Hardware Settings"
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config ESP_ENABLE_PVT
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bool "Auto adjust hp & lp voltage using pvt function (MUST ENABLE FOR MP)"
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depends on SOC_PMU_PVT_SUPPORTED
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default n if IDF_TARGET_ESP32C6
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default y
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help
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If enabled, hp & lp voltage can be auto adjust by PVT characteristic.
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@@ -47,7 +47,7 @@ entries:
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elif PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32P4 != y:
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pmu_param:get_act_hp_dbias (noflash)
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pmu_param:get_act_lp_dbias (noflash)
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if SOC_PMU_PVT_SUPPORTED = y:
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if SOC_PMU_PVT_SUPPORTED = y && ESP_ENABLE_PVT = y:
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pmu_pvt (noflash)
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if PM_SLP_IRAM_OPT = y && SOC_USB_SERIAL_JTAG_SUPPORTED = y:
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sleep_console (noflash)
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@@ -83,7 +83,7 @@ void pvt_auto_dbias_init(void)
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SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
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/*config for dbias func*/
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CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN);
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esp_rom_delay_us(100);
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esp_rom_delay_us(1);
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SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S);
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SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S); // Select monitor cell ,which used to monitor PVT situation
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SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S);
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@@ -130,7 +130,6 @@ void IRAM_ATTR pvt_func_enable(bool enable)
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SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
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SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, pvt_lp_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
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CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias
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CLEAR_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN);
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SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
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CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
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CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -215,6 +215,8 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
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static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
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pvt_auto_dbias_init();
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charge_pump_init();
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pvt_func_enable(true);
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charge_pump_enable(true);
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#endif
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@@ -353,10 +355,6 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
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void rtc_clk_cpu_freq_set_xtal(void)
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{
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rtc_clk_cpu_set_to_default_config();
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#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
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charge_pump_enable(false);
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pvt_func_enable(false);
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#endif
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rtc_clk_bbpll_disable();
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}
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@@ -793,7 +793,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
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regi2c_tsens_reg_read();
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#endif
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}
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#if CONFIG_ESP_ENABLE_PVT
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#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
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pvt_func_enable(false);
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#endif
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@@ -810,7 +810,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
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*/
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static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
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{
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#if CONFIG_ESP_ENABLE_PVT
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#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
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pvt_func_enable(true);
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#endif
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@@ -168,7 +168,7 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
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err = sleep_pau_retention_init();
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if(err) goto error;
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#endif
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#if CONFIG_ESP_ENABLE_PVT
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#if CONFIG_ESP_ENABLE_PVT && SOC_PVT_RETENTION_BY_REGDMA
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err = sleep_pvt_retention_init();
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if(err) goto error;
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#endif
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