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bugfix: fix wifi loss packet and missing interrupt issues when switching root clock source

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This commit is contained in:
sibeibei
2026-05-12 15:37:53 +08:00
parent aa2bd15d46
commit 1d16c0fbad
5 changed files with 37 additions and 0 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
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@@ -1543,6 +1543,10 @@ config SOC_RCC_IS_INDEPENDENT
bool
default y
config SOC_CLK_ROOT_CLK_SWITCH_PROTECT
bool
default y
config SOC_CLK_ANA_I2C_MST_DEPENDS_ON_MODEM_APB
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+2
View File
@@ -625,6 +625,8 @@
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
#define SOC_CLK_ROOT_CLK_SWITCH_PROTECT 1 /*!< Need to bypass root clock auto gating during 240M/160M PLL switch */
#define SOC_CLK_ANA_I2C_MST_DEPENDS_ON_MODEM_APB (1) /*!< Analog I2C master clock depends on CLK_160M_REF on clock tree */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/