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Merge branch 'feature/support_efuse_for_esp32h2' into 'master'

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efuse: Add support for esp32h2

Closes IDF-6252, IDF-4337, and IDF-6897

See merge request espressif/esp-idf!22393
This commit is contained in:
morris
2023-02-22 13:41:40 +08:00
parent 778aeae99e f3394c488a
commit 1c9b96ab37
25 changed files with 1408 additions and 1086 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -507,6 +507,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 1
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default y
config SOC_EFUSE_DIS_PAD_JTAG
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
+1
View File
@@ -243,6 +243,7 @@
#define SOC_TIMER_GROUP_TOTAL_TIMERS (1U)
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_PAD_JTAG 1
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -747,6 +747,10 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default y
config SOC_EFUSE_DIS_PAD_JTAG
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
+1
View File
@@ -334,6 +334,7 @@
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_PAD_JTAG 1
#define SOC_EFUSE_DIS_USB_JTAG 1
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -895,6 +895,10 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default y
config SOC_EFUSE_DIS_PAD_JTAG
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+1
View File
@@ -374,6 +374,7 @@
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_PAD_JTAG 1
#define SOC_EFUSE_DIS_USB_JTAG 1
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
components/soc/esp32h2/include/soc/efuse_defs.h
+17
View File
@@ -0,0 +1,17 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif
components/soc/esp32h2/include/soc/efuse_reg.h
+145 -78
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "efuse_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -220,17 +221,16 @@ extern "C" {
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13
/** EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0;
/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
* Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
*/
#define EFUSE_DIS_CAN (BIT(14))
#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S)
#define EFUSE_DIS_CAN_V 0x00000001U
#define EFUSE_DIS_CAN_S 14
#define EFUSE_DIS_TWAI (BIT(14))
#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
#define EFUSE_DIS_TWAI_V 0x00000001U
#define EFUSE_DIS_TWAI_S 14
/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
* Represents whether the selection between usb_to_jtag and pad_to_jtag through
* strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
* is enabled or disabled. 1: enabled. 0: disabled.
* Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
* strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
*/
#define EFUSE_JTAG_SEL_ENABLE (BIT(15))
#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
@@ -481,14 +481,13 @@ extern "C" {
#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U
#define EFUSE_DIS_DIRECT_BOOT_S 1
/** EFUSE_DIS_USB_PRINT : RO; bitpos: [2]; default: 0;
* Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
* 0: enabled.
/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
* Set this bit to disable USB-Serial-JTAG print during rom boot.
*/
#define EFUSE_DIS_USB_PRINT (BIT(2))
#define EFUSE_DIS_USB_PRINT_M (EFUSE_DIS_USB_PRINT_V << EFUSE_DIS_USB_PRINT_S)
#define EFUSE_DIS_USB_PRINT_V 0x00000001U
#define EFUSE_DIS_USB_PRINT_S 2
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2))
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2
/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
* Reserved.
*/
@@ -545,8 +544,7 @@ extern "C" {
#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U
#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25
/** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0;
* Represents whether the hysteresis function of corresponding PAD is enabled. 1:
* enabled. 0:disabled.
* Set bits to enable hysteresis function of PAD0~5
*/
#define EFUSE_HYS_EN_PAD0 0x0000003FU
#define EFUSE_HYS_EN_PAD0_M (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S)
@@ -558,8 +556,7 @@ extern "C" {
*/
#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
/** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0;
* Represents whether the hysteresis function of corresponding PAD is enabled. 1:
* enabled. 0:disabled.
* Set bits to enable hysteresis function of PAD6~27
*/
#define EFUSE_HYS_EN_PAD1 0x003FFFFFU
#define EFUSE_HYS_EN_PAD1_M (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S)
@@ -641,25 +638,57 @@ extern "C" {
#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU
#define EFUSE_MAC_RESERVED_2_S 0
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
* Stores the first 14 bits of the zeroth part of system data.
/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [20:18]; default: 0; */
#define EFUSE_WAFER_VERSION_MINOR 0x00000007U
#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
#define EFUSE_WAFER_VERSION_MINOR_V 0x00000007U
#define EFUSE_WAFER_VERSION_MINOR_S 18
/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [22:21]; default: 0; */
#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
#define EFUSE_WAFER_VERSION_MAJOR_S 21
/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [23]; default: 0;
* Disables check of wafer version major
*/
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_S 18
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(23))
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 23
/** EFUSE_FLASH_CAP : R; bitpos: [26:24]; default: 0; */
#define EFUSE_FLASH_CAP 0x00000007U
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
#define EFUSE_FLASH_CAP_V 0x00000007U
#define EFUSE_FLASH_CAP_S 24
/** EFUSE_FLASH_TEMP : R; bitpos: [28:27]; default: 0; */
#define EFUSE_FLASH_TEMP 0x00000003U
#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
#define EFUSE_FLASH_TEMP_V 0x00000003U
#define EFUSE_FLASH_TEMP_S 27
/** EFUSE_FLASH_VENDOR : R; bitpos: [31:29]; default: 0; */
#define EFUSE_FLASH_VENDOR 0x00000007U
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
#define EFUSE_FLASH_VENDOR_V 0x00000007U
#define EFUSE_FLASH_VENDOR_S 29
/** EFUSE_RD_MAC_SYS_4_REG register
* BLOCK1 data register $n.
*/
#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the zeroth part of system data.
/** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0;
* Package version
*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_S 0
#define EFUSE_PKG_VERSION 0x00000007U
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
#define EFUSE_PKG_VERSION_V 0x00000007U
#define EFUSE_PKG_VERSION_S 0
/** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_131 0x1FFFFFFFU
#define EFUSE_RESERVED_1_131_M (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S)
#define EFUSE_RESERVED_1_131_V 0x1FFFFFFFU
#define EFUSE_RESERVED_1_131_S 3
/** EFUSE_RD_MAC_SYS_5_REG register
* BLOCK1 data register $n.
@@ -677,61 +706,89 @@ extern "C" {
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
* Stores the zeroth 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_0_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
/** EFUSE_RD_SYS_PART1_DATA1_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_1_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
/** EFUSE_RD_SYS_PART1_DATA2_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_2_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
/** EFUSE_RD_SYS_PART1_DATA3_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
* Stores the third 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_3_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
/** EFUSE_RD_SYS_PART1_DATA4_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
* Stores the fourth 32 bits of the first part of system data.
/** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0;
* reserved
*/
#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_4_S 0
#define EFUSE_RESERVED_2_128 0x00000003U
#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
#define EFUSE_RESERVED_2_128_V 0x00000003U
#define EFUSE_RESERVED_2_128_S 0
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0;
* BLK_VERSION_MINOR of BLOCK2
*/
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_S 2
/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0;
* BLK_VERSION_MAJOR of BLOCK2
*/
#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
#define EFUSE_BLK_VERSION_MAJOR_S 5
/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
* Disables check of blk version major
*/
#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7))
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7
/** EFUSE_RESERVED_2_136 : R; bitpos: [31:8]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_2_136 0x00FFFFFFU
#define EFUSE_RESERVED_2_136_M (EFUSE_RESERVED_2_136_V << EFUSE_RESERVED_2_136_S)
#define EFUSE_RESERVED_2_136_V 0x00FFFFFFU
#define EFUSE_RESERVED_2_136_S 8
/** EFUSE_RD_SYS_PART1_DATA5_REG register
* Register $n of BLOCK2 (system).
@@ -845,25 +902,39 @@ extern "C" {
* Register $n of BLOCK3 (user).
*/
#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of BLOCK3 (user).
/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
* reserved
*/
#define EFUSE_USR_DATA6 0xFFFFFFFFU
#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
#define EFUSE_USR_DATA6_V 0xFFFFFFFFU
#define EFUSE_USR_DATA6_S 0
#define EFUSE_RESERVED_3_192 0x000000FFU
#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
#define EFUSE_RESERVED_3_192_V 0x000000FFU
#define EFUSE_RESERVED_3_192_S 0
/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
* Custom MAC
*/
#define EFUSE_CUSTOM_MAC 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_S 8
/** EFUSE_RD_USR_DATA7_REG register
* Register $n of BLOCK3 (user).
*/
#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of BLOCK3 (user).
/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
* Custom MAC
*/
#define EFUSE_USR_DATA7 0xFFFFFFFFU
#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
#define EFUSE_USR_DATA7_V 0xFFFFFFFFU
#define EFUSE_USR_DATA7_S 0
#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_1_S 0
/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_3_248 0x000000FFU
#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
#define EFUSE_RESERVED_3_248_V 0x000000FFU
#define EFUSE_RESERVED_3_248_S 24
/** EFUSE_RD_KEY0_DATA0_REG register
* Register $n of BLOCK4 (KEY0).
@@ -2137,10 +2208,6 @@ extern "C" {
#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
#define EFUSE_OP_CODE_V 0x0000FFFFU
#define EFUSE_OP_CODE_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
* Configures which block to use for ECDSA key output.
*/
components/soc/esp32h2/include/soc/efuse_struct.h
+204 -160
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -155,7 +155,7 @@ typedef union {
} efuse_pgm_check_value2_reg_t;
/** Group: ******** Registers */
/** Group: Read Data Register */
/** Type of rd_wr_dis register
* BLOCK0 data register 0.
*/
@@ -211,14 +211,13 @@ typedef union {
* enabled. 1: disabled. 0: enabled.
*/
uint32_t spi_download_mspi_dis:1;
/** dis_can : RO; bitpos: [14]; default: 0;
/** dis_twai : RO; bitpos: [14]; default: 0;
* Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
*/
uint32_t dis_can:1;
uint32_t dis_twai:1;
/** jtag_sel_enable : RO; bitpos: [15]; default: 0;
* Represents whether the selection between usb_to_jtag and pad_to_jtag through
* strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
* is enabled or disabled. 1: enabled. 0: disabled.
* Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
* strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
*/
uint32_t jtag_sel_enable:1;
/** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
@@ -385,11 +384,10 @@ typedef union {
* Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
*/
uint32_t dis_direct_boot:1;
/** dis_usb_print : RO; bitpos: [2]; default: 0;
* Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
* 0: enabled.
/** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
* Set this bit to disable USB-Serial-JTAG print during rom boot.
*/
uint32_t dis_usb_print:1;
uint32_t dis_usb_serial_jtag_rom_print:1;
/** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
* Reserved.
*/
@@ -425,8 +423,7 @@ typedef union {
*/
uint32_t secure_boot_disable_fast_wake:1;
/** hys_en_pad0 : RO; bitpos: [31:26]; default: 0;
* Represents whether the hysteresis function of corresponding PAD is enabled. 1:
* enabled. 0:disabled.
* Set bits to enable hysteresis function of PAD0~5
*/
uint32_t hys_en_pad0:6;
};
@@ -439,8 +436,7 @@ typedef union {
typedef union {
struct {
/** hys_en_pad1 : RO; bitpos: [21:0]; default: 0;
* Represents whether the hysteresis function of corresponding PAD is enabled. 1:
* enabled. 0:disabled.
* Set bits to enable hysteresis function of PAD6~27
*/
uint32_t hys_en_pad1:22;
/** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0;
@@ -511,10 +507,20 @@ typedef union {
* Reserved.
*/
uint32_t mac_reserved_2:18;
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
* Stores the first 14 bits of the zeroth part of system data.
/** wafer_version_minor : R; bitpos: [20:18]; default: 0; */
uint32_t wafer_version_minor:3;
/** wafer_version_major : R; bitpos: [22:21]; default: 0; */
uint32_t wafer_version_major:2;
/** disable_wafer_version_major : R; bitpos: [23]; default: 0;
* Disables check of wafer version major
*/
uint32_t sys_data_part0_0:14;
uint32_t disable_wafer_version_major:1;
/** flash_cap : R; bitpos: [26:24]; default: 0; */
uint32_t flash_cap:3;
/** flash_temp : R; bitpos: [28:27]; default: 0; */
uint32_t flash_temp:2;
/** flash_vendor : R; bitpos: [31:29]; default: 0; */
uint32_t flash_vendor:3;
};
uint32_t val;
} efuse_rd_mac_sys_3_reg_t;
@@ -524,10 +530,14 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the zeroth part of system data.
/** pkg_version : R; bitpos: [2:0]; default: 0;
* Package version
*/
uint32_t sys_data_part0_1:32;
uint32_t pkg_version:3;
/** reserved_1_131 : R; bitpos: [31:3]; default: 0;
* reserved
*/
uint32_t reserved_1_131:29;
};
uint32_t val;
} efuse_rd_mac_sys_4_reg_t;
@@ -550,10 +560,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
* Stores the zeroth 32 bits of the first part of system data.
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_0:32;
uint32_t optional_unique_id:32;
};
uint32_t val;
} efuse_rd_sys_part1_data0_reg_t;
@@ -563,10 +573,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the first part of system data.
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_1:32;
uint32_t optional_unique_id_1:32;
};
uint32_t val;
} efuse_rd_sys_part1_data1_reg_t;
@@ -576,10 +586,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the first part of system data.
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_2:32;
uint32_t optional_unique_id_2:32;
};
uint32_t val;
} efuse_rd_sys_part1_data2_reg_t;
@@ -589,10 +599,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
* Stores the third 32 bits of the first part of system data.
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_3:32;
uint32_t optional_unique_id_3:32;
};
uint32_t val;
} efuse_rd_sys_part1_data3_reg_t;
@@ -602,10 +612,26 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
* Stores the fourth 32 bits of the first part of system data.
/** reserved_2_128 : R; bitpos: [1:0]; default: 0;
* reserved
*/
uint32_t sys_data_part1_4:32;
uint32_t reserved_2_128:2;
/** blk_version_minor : R; bitpos: [4:2]; default: 0;
* BLK_VERSION_MINOR of BLOCK2
*/
uint32_t blk_version_minor:3;
/** blk_version_major : R; bitpos: [6:5]; default: 0;
* BLK_VERSION_MAJOR of BLOCK2
*/
uint32_t blk_version_major:2;
/** disable_blk_version_major : R; bitpos: [7]; default: 0;
* Disables check of blk version major
*/
uint32_t disable_blk_version_major:1;
/** reserved_2_136 : R; bitpos: [31:8]; default: 0;
* reserved
*/
uint32_t reserved_2_136:24;
};
uint32_t val;
} efuse_rd_sys_part1_data4_reg_t;
@@ -732,10 +758,14 @@ typedef union {
*/
typedef union {
struct {
/** usr_data6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of BLOCK3 (user).
/** reserved_3_192 : R; bitpos: [7:0]; default: 0;
* reserved
*/
uint32_t usr_data6:32;
uint32_t reserved_3_192:8;
/** custom_mac : R; bitpos: [31:8]; default: 0;
* Custom MAC
*/
uint32_t custom_mac:24;
};
uint32_t val;
} efuse_rd_usr_data6_reg_t;
@@ -745,10 +775,14 @@ typedef union {
*/
typedef union {
struct {
/** usr_data7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of BLOCK3 (user).
/** custom_mac_1 : R; bitpos: [23:0]; default: 0;
* Custom MAC
*/
uint32_t usr_data7:32;
uint32_t custom_mac_1:24;
/** reserved_3_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
uint32_t reserved_3_248:8;
};
uint32_t val;
} efuse_rd_usr_data7_reg_t;
@@ -1481,6 +1515,8 @@ typedef union {
uint32_t val;
} efuse_rd_sys_part2_data7_reg_t;
/** Group: Report Register */
/** Type of rd_repeat_err0 register
* Programming error record register 0 of BLOCK0.
*/
@@ -1847,6 +1883,8 @@ typedef union {
uint32_t val;
} efuse_rd_rs_err1_reg_t;
/** Group: Configuration Register */
/** Type of clk register
* eFuse clcok configuration register.
*/
@@ -1892,52 +1930,6 @@ typedef union {
uint32_t val;
} efuse_conf_reg_t;
/** Type of status register
* eFuse status register.
*/
typedef union {
struct {
/** state : RO; bitpos: [3:0]; default: 0;
* Indicates the state of the eFuse state machine.
*/
uint32_t state:4;
/** otp_load_sw : RO; bitpos: [4]; default: 0;
* The value of OTP_LOAD_SW.
*/
uint32_t otp_load_sw:1;
/** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
* The value of OTP_VDDQ_C_SYNC2.
*/
uint32_t otp_vddq_c_sync2:1;
/** otp_strobe_sw : RO; bitpos: [6]; default: 0;
* The value of OTP_STROBE_SW.
*/
uint32_t otp_strobe_sw:1;
/** otp_csb_sw : RO; bitpos: [7]; default: 0;
* The value of OTP_CSB_SW.
*/
uint32_t otp_csb_sw:1;
/** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
* The value of OTP_PGENB_SW.
*/
uint32_t otp_pgenb_sw:1;
/** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
* The value of OTP_VDDQ_IS_SW.
*/
uint32_t otp_vddq_is_sw:1;
/** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
* Indicates the number of block valid bit.
*/
uint32_t blk0_valid_bit_cnt:10;
/** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
* Indicates which block is used for ECDSA key output.
*/
uint32_t cur_ecdsa_blk:4;
uint32_t reserved_24:8;
};
uint32_t val;
} efuse_status_reg_t;
/** Type of cmd register
* eFuse command register.
*/
@@ -1961,78 +1953,6 @@ typedef union {
uint32_t val;
} efuse_cmd_reg_t;
/** Type of int_raw register
* eFuse raw interrupt register.
*/
typedef union {
struct {
/** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw bit signal for read_done interrupt.
*/
uint32_t read_done_int_raw:1;
/** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw bit signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_raw_reg_t;
/** Type of int_st register
* eFuse interrupt status register.
*/
typedef union {
struct {
/** read_done_int_st : RO; bitpos: [0]; default: 0;
* The status signal for read_done interrupt.
*/
uint32_t read_done_int_st:1;
/** pgm_done_int_st : RO; bitpos: [1]; default: 0;
* The status signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_st_reg_t;
/** Type of int_ena register
* eFuse interrupt enable register.
*/
typedef union {
struct {
/** read_done_int_ena : R/W; bitpos: [0]; default: 0;
* The enable signal for read_done interrupt.
*/
uint32_t read_done_int_ena:1;
/** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
* The enable signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_ena_reg_t;
/** Type of int_clr register
* eFuse interrupt clear register.
*/
typedef union {
struct {
/** read_done_int_clr : WT; bitpos: [0]; default: 0;
* The clear signal for read_done interrupt.
*/
uint32_t read_done_int_clr:1;
/** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
* The clear signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_clr_reg_t;
/** Type of dac_conf register
* Controls the eFuse programming voltage.
*/
@@ -2149,6 +2069,130 @@ typedef union {
uint32_t val;
} efuse_wr_tim_conf0_rs_bypass_reg_t;
/** Group: Status Register */
/** Type of status register
* eFuse status register.
*/
typedef union {
struct {
/** state : RO; bitpos: [3:0]; default: 0;
* Indicates the state of the eFuse state machine.
*/
uint32_t state:4;
/** otp_load_sw : RO; bitpos: [4]; default: 0;
* The value of OTP_LOAD_SW.
*/
uint32_t otp_load_sw:1;
/** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
* The value of OTP_VDDQ_C_SYNC2.
*/
uint32_t otp_vddq_c_sync2:1;
/** otp_strobe_sw : RO; bitpos: [6]; default: 0;
* The value of OTP_STROBE_SW.
*/
uint32_t otp_strobe_sw:1;
/** otp_csb_sw : RO; bitpos: [7]; default: 0;
* The value of OTP_CSB_SW.
*/
uint32_t otp_csb_sw:1;
/** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
* The value of OTP_PGENB_SW.
*/
uint32_t otp_pgenb_sw:1;
/** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
* The value of OTP_VDDQ_IS_SW.
*/
uint32_t otp_vddq_is_sw:1;
/** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
* Indicates the number of block valid bit.
*/
uint32_t blk0_valid_bit_cnt:10;
/** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
* Indicates which block is used for ECDSA key output.
*/
uint32_t cur_ecdsa_blk:4;
uint32_t reserved_24:8;
};
uint32_t val;
} efuse_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* eFuse raw interrupt register.
*/
typedef union {
struct {
/** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw bit signal for read_done interrupt.
*/
uint32_t read_done_int_raw:1;
/** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw bit signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_raw_reg_t;
/** Type of int_st register
* eFuse interrupt status register.
*/
typedef union {
struct {
/** read_done_int_st : RO; bitpos: [0]; default: 0;
* The status signal for read_done interrupt.
*/
uint32_t read_done_int_st:1;
/** pgm_done_int_st : RO; bitpos: [1]; default: 0;
* The status signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_st_reg_t;
/** Type of int_ena register
* eFuse interrupt enable register.
*/
typedef union {
struct {
/** read_done_int_ena : R/W; bitpos: [0]; default: 0;
* The enable signal for read_done interrupt.
*/
uint32_t read_done_int_ena:1;
/** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
* The enable signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_ena_reg_t;
/** Type of int_clr register
* eFuse interrupt clear register.
*/
typedef union {
struct {
/** read_done_int_clr : WT; bitpos: [0]; default: 0;
* The clear signal for read_done interrupt.
*/
uint32_t read_done_int_clr:1;
/** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
* The clear signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* eFuse version register.
*/
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -831,6 +831,10 @@ config SOC_AES_SUPPORT_GCM
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_DCACHE
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
+1
View File
@@ -365,6 +365,7 @@
#define SOC_AES_SUPPORT_GCM (1)
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
#define SOC_EFUSE_HARD_DIS_JTAG 1
#define SOC_EFUSE_SOFT_DIS_JTAG 1
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -1039,6 +1039,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_DCACHE
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
+1
View File
@@ -425,6 +425,7 @@
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
#define SOC_EFUSE_HARD_DIS_JTAG 1
#define SOC_EFUSE_DIS_USB_JTAG 1