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refactor(esp_system): clear dependency on hal components

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This commit is contained in:
Chen Chen
2025-12-16 09:11:59 +08:00
parent bc646511dd
commit 1b015d22eb
30 changed files with 970 additions and 884 deletions
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components/soc/esp32h4/register/soc/trace_reg.h
+21 -19
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@@ -11,10 +11,12 @@
extern "C" {
#endif
#define REG_TRACE_BASE(i) (DR_REG_TRACE0_BASE + (i) * 0x1000)
/** TRACE_MEM_START_ADDR_REG register
* Memory start address
*/
#define TRACE_MEM_START_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x0)
#define TRACE_MEM_START_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x0)
/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
* Configures the start address of the trace memory
*/
@@ -26,7 +28,7 @@ extern "C" {
/** TRACE_MEM_END_ADDR_REG register
* Memory end address
*/
#define TRACE_MEM_END_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x4)
#define TRACE_MEM_END_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x4)
/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
* Configures the end address of the trace memory.
*/
@@ -38,7 +40,7 @@ extern "C" {
/** TRACE_MEM_CURRENT_ADDR_REG register
* Memory current addr
*/
#define TRACE_MEM_CURRENT_ADDR_REG(i) (DR_REG_TRACE_BASE(i) + 0x8)
#define TRACE_MEM_CURRENT_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x8)
/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* Represents the current memory address for writing.
*/
@@ -50,7 +52,7 @@ extern "C" {
/** TRACE_MEM_ADDR_UPDATE_REG register
* Memory address update
*/
#define TRACE_MEM_ADDR_UPDATE_REG(i) (DR_REG_TRACE_BASE(i) + 0xc)
#define TRACE_MEM_ADDR_UPDATE_REG(i) (REG_TRACE_BASE(i) + 0xc)
/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Configures whether to update the value of
* \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
@@ -66,7 +68,7 @@ extern "C" {
/** TRACE_FIFO_STATUS_REG register
* FIFO status register
*/
#define TRACE_FIFO_STATUS_REG(i) (DR_REG_TRACE_BASE(i) + 0x10)
#define TRACE_FIFO_STATUS_REG(i) (REG_TRACE_BASE(i) + 0x10)
/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
* Represent whether the FIFO is empty.
* 1: Empty
@@ -91,7 +93,7 @@ extern "C" {
/** TRACE_INTR_ENA_REG register
* Interrupt enable register
*/
#define TRACE_INTR_ENA_REG(i) (DR_REG_TRACE_BASE(i) + 0x14)
#define TRACE_INTR_ENA_REG(i) (REG_TRACE_BASE(i) + 0x14)
/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TRACE_FIFO_OVERFLOW_INTR
*/
@@ -110,7 +112,7 @@ extern "C" {
/** TRACE_INTR_RAW_REG register
* Interrupt raw status register
*/
#define TRACE_INTR_RAW_REG(i) (DR_REG_TRACE_BASE(i) + 0x18)
#define TRACE_INTR_RAW_REG(i) (REG_TRACE_BASE(i) + 0x18)
/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
* The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.
*/
@@ -129,7 +131,7 @@ extern "C" {
/** TRACE_INTR_CLR_REG register
* Interrupt clear register
*/
#define TRACE_INTR_CLR_REG(i) (DR_REG_TRACE_BASE(i) + 0x1c)
#define TRACE_INTR_CLR_REG(i) (REG_TRACE_BASE(i) + 0x1c)
/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear TRACE_FIFO_OVERFLOW_INTR
*/
@@ -148,7 +150,7 @@ extern "C" {
/** TRACE_TRIGGER_REG register
* Trace enable register
*/
#define TRACE_TRIGGER_REG(i) (DR_REG_TRACE_BASE(i) + 0x20)
#define TRACE_TRIGGER_REG(i) (REG_TRACE_BASE(i) + 0x20)
/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
* Configure whether to enable the encoder.
* 0: Invalid
@@ -189,7 +191,7 @@ extern "C" {
/** TRACE_CONFIG_REG register
* trace configuration register
*/
#define TRACE_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x24)
#define TRACE_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x24)
/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
* Configure whether to enable the trigger signal.
* 0: Disable
@@ -251,7 +253,7 @@ extern "C" {
/** TRACE_FILTER_CONTROL_REG register
* filter control register
*/
#define TRACE_FILTER_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x28)
#define TRACE_FILTER_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x28)
/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
* Configure whether to enable filtering.
* 0: Disable, always match.
@@ -306,7 +308,7 @@ extern "C" {
/** TRACE_FILTER_MATCH_CONTROL_REG register
* filter match control register
*/
#define TRACE_FILTER_MATCH_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x2c)
#define TRACE_FILTER_MATCH_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x2c)
/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
* Configures the privilege level for matching. Valid only when
* \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set.
@@ -338,7 +340,7 @@ extern "C" {
/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
* filter comparator match control register
*/
#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (DR_REG_TRACE_BASE(i) + 0x30)
#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x30)
/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
* Configures the input of the primary comparator for matching:
* 0: iaddr
@@ -419,7 +421,7 @@ extern "C" {
/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
* primary comparator match value
*/
#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x34)
#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x34)
/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
* Configures the match value for the primary comparator
*/
@@ -431,7 +433,7 @@ extern "C" {
/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
* secondary comparator match value
*/
#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (DR_REG_TRACE_BASE(i) + 0x38)
#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x38)
/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
* Configures the match value for the secondary comparator
*/
@@ -443,7 +445,7 @@ extern "C" {
/** TRACE_RESYNC_PROLONGED_REG register
* Resync configuration register
*/
#define TRACE_RESYNC_PROLONGED_REG(i) (DR_REG_TRACE_BASE(i) + 0x3c)
#define TRACE_RESYNC_PROLONGED_REG(i) (REG_TRACE_BASE(i) + 0x3c)
/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
* Configures the threshold for synchronization counter
*/
@@ -466,7 +468,7 @@ extern "C" {
/** TRACE_AHB_CONFIG_REG register
* AHB config register
*/
#define TRACE_AHB_CONFIG_REG(i) (DR_REG_TRACE_BASE(i) + 0x40)
#define TRACE_AHB_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x40)
/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
* Configures the AHB burst mode.
* 0: SINGLE
@@ -490,7 +492,7 @@ extern "C" {
/** TRACE_CLOCK_GATE_REG register
* Clock gate control register
*/
#define TRACE_CLOCK_GATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x44)
#define TRACE_CLOCK_GATE_REG(i) (REG_TRACE_BASE(i) + 0x44)
/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures register clock gating.
* 0: Support clock only when the application writes registers to save power.
@@ -505,7 +507,7 @@ extern "C" {
/** TRACE_DATE_REG register
* Version control register
*/
#define TRACE_DATE_REG(i) (DR_REG_TRACE_BASE(i) + 0x3fc)
#define TRACE_DATE_REG(i) (REG_TRACE_BASE(i) + 0x3fc)
/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
* Version control register.
*/