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https://github.com/espressif/esp-idf.git
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feat(esp_riscv_trace): add ESP32-C5 support
This commit is contained in:
Erhan Kurubas
@@ -0,0 +1,254 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/trace_reg.h"
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#include "soc/trace_struct.h"
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#include "soc/pcr_struct.h"
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#include "hal/assert.h"
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#include "hal/riscv_trace_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @brief Return the register block for the given core. */
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static inline trace_dev_t *riscv_trace_ll_get_hw(int core)
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{
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HAL_ASSERT(core == 0);
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(void)core;
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return &TRACE;
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}
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/*---------------------------------------------------------------------------
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* Clock and reset
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*--------------------------------------------------------------------------*/
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/** @brief Enable or disable the TRACE clock. */
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static inline void riscv_trace_ll_enable_bus_clock(bool enable)
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{
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PCR.trace_conf.trace_clk_en = enable;
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}
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/** @brief Assert and release the reset of the encoder. */
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static inline void riscv_trace_ll_reset_register(int core)
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{
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(void)core;
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PCR.trace_conf.trace_rst_en = 1;
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PCR.trace_conf.trace_rst_en = 0;
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}
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/** @brief Enable the per-module register clock gate. */
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static inline void riscv_trace_ll_enable_module_clock(trace_dev_t *hw, bool enable)
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{
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hw->clock_gate.clk_en = enable;
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}
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/*---------------------------------------------------------------------------
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* Memory configuration
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_mem_start_addr(trace_dev_t *hw, uint32_t addr)
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{
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hw->mem_start_addr.mem_start_addr = addr;
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}
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static inline void riscv_trace_ll_set_mem_end_addr(trace_dev_t *hw, uint32_t addr)
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{
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hw->mem_end_addr.mem_end_addr = addr;
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}
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static inline uint32_t riscv_trace_ll_get_mem_current_addr(trace_dev_t *hw)
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{
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return hw->mem_current_addr.mem_current_addr;
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}
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/** @brief Reload the current address from the start address. */
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static inline void riscv_trace_ll_update_mem_current_addr(trace_dev_t *hw)
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{
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hw->mem_addr_update.mem_current_addr_update = 1;
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}
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/*---------------------------------------------------------------------------
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* Status
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*--------------------------------------------------------------------------*/
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static inline uint32_t riscv_trace_ll_get_fifo_status(trace_dev_t *hw)
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{
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return hw->fifo_status.val;
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}
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/*---------------------------------------------------------------------------
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* Trigger, loop mode and restart
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_trigger_on(trace_dev_t *hw)
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{
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hw->trigger.trigger_on = 1;
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}
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static inline void riscv_trace_ll_trigger_off(trace_dev_t *hw)
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{
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hw->trigger.trigger_off = 1;
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}
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static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
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{
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hw->trigger.mem_loop = loop;
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}
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static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
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{
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hw->trigger.restart_ena = enable;
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}
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/*---------------------------------------------------------------------------
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* Encoder options (config register)
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_full_address(trace_dev_t *hw, bool full)
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{
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hw->config.full_address = full;
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}
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static inline void riscv_trace_ll_set_stall_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.stall_ena = enable;
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}
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static inline void riscv_trace_ll_set_halt_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.halt_ena = enable;
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}
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static inline void riscv_trace_ll_set_reset_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.reset_ena = enable;
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}
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static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.dm_trigger_ena = enable;
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}
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/*---------------------------------------------------------------------------
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* Resynchronization
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
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{
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hw->resync_prolonged.resync_mode = mode;
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}
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static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
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{
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hw->resync_prolonged.resync_prolonged = threshold;
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}
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/*---------------------------------------------------------------------------
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* AHB configuration
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_ahb_burst(trace_dev_t *hw, uint32_t hburst)
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{
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hw->ahb_config.hburst = hburst;
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}
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static inline void riscv_trace_ll_set_ahb_max_incr(trace_dev_t *hw, uint32_t max_incr)
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{
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hw->ahb_config.max_incr = max_incr;
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}
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/*---------------------------------------------------------------------------
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* Interrupts
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_intr_ena(trace_dev_t *hw, uint32_t mask)
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{
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hw->intr_ena.val = mask;
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}
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static inline uint32_t riscv_trace_ll_get_intr_raw(trace_dev_t *hw)
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{
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return hw->intr_raw.val;
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}
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static inline void riscv_trace_ll_clear_intr(trace_dev_t *hw, uint32_t mask)
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{
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hw->intr_clr.val = mask;
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}
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/*---------------------------------------------------------------------------
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* Filter unit
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_filter_en(trace_dev_t *hw, bool enable)
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{
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hw->filter_control.filter_en = enable;
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}
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static inline void riscv_trace_ll_set_filter_control(trace_dev_t *hw, bool match_comp,
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bool match_privilege, bool match_ecause,
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bool match_interrupt)
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{
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hw->filter_control.match_comp = match_comp;
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hw->filter_control.match_privilege = match_privilege;
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hw->filter_control.match_ecause = match_ecause;
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hw->filter_control.match_interrupt = match_interrupt;
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}
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static inline bool riscv_trace_ll_priv_is_supported(uint32_t priv)
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{
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return priv == RISCV_TRACE_PRIV_USER || priv == RISCV_TRACE_PRIV_MACHINE;
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}
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static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, uint32_t priv_choice,
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bool intr_value, uint32_t ecause_choice)
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{
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// This target has no supervisor mode, so the selector is 1 bit: 0 = user, 1 = machine.
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hw->filter_match_control.match_choice_privilege = (priv_choice == RISCV_TRACE_PRIV_MACHINE);
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hw->filter_match_control.match_value_interrupt = intr_value;
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hw->filter_match_control.match_choice_ecause = ecause_choice;
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}
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static inline void riscv_trace_ll_set_p_comparator(trace_dev_t *hw, uint32_t input,
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uint32_t function, bool notify)
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{
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hw->filter_comparator_control.p_input = input;
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hw->filter_comparator_control.p_function = function;
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hw->filter_comparator_control.p_notify = notify;
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}
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static inline void riscv_trace_ll_set_s_comparator(trace_dev_t *hw, uint32_t input,
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uint32_t function, bool notify)
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{
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hw->filter_comparator_control.s_input = input;
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hw->filter_comparator_control.s_function = function;
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hw->filter_comparator_control.s_notify = notify;
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}
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static inline void riscv_trace_ll_set_match_mode(trace_dev_t *hw, uint32_t mode)
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{
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hw->filter_comparator_control.match_mode = mode;
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}
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static inline void riscv_trace_ll_set_p_match_value(trace_dev_t *hw, uint32_t value)
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{
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hw->filter_p_comparator_match.p_match = value;
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}
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static inline void riscv_trace_ll_set_s_match_value(trace_dev_t *hw, uint32_t value)
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{
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hw->filter_s_comparator_match.s_match = value;
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}
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#ifdef __cplusplus
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}
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#endif
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