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https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
fix(esp_driver_gptimer): do gptimer retention by timer unit rather than timer group
This commit is contained in:
wuzhenghui
@@ -22,10 +22,10 @@ typedef enum periph_retention_module {
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* TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
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SLEEP_RETENTION_MODULE_SYS_PERIPH = 3,
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_TG0_WDT = 4,
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SLEEP_RETENTION_MODULE_TG0_WDT = 4,
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SLEEP_RETENTION_MODULE_TG1_WDT = 5,
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SLEEP_RETENTION_MODULE_TG0_TIMER = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER = 7,
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SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7,
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_GDMA_CH0 = 8,
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SLEEP_RETENTION_MODULE_GDMA_CH1 = 9,
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@@ -54,8 +54,8 @@ typedef enum periph_retention_module_bitmap {
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_BM_TASK_WDT = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
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SLEEP_RETENTION_MODULE_BM_INT_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER0),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER0),
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
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SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
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@@ -76,8 +76,8 @@ typedef enum periph_retention_module_bitmap {
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#define TOP_DOMAIN_PERIPHERALS_BM (SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
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| SLEEP_RETENTION_MODULE_BM_TASK_WDT \
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| SLEEP_RETENTION_MODULE_BM_INT_WDT \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH1 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH2 \
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@@ -80,13 +80,20 @@ const regdma_entries_config_t tg1_timer_regs_retention[] = {
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[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
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};
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const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
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[1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
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};
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const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)},
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[1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)},
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
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[0] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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}
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},
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[1] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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}
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},
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};
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#endif
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@@ -80,13 +80,20 @@ const regdma_entries_config_t tg1_timer_regs_retention[] = {
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[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
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};
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const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
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[1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
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};
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const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)},
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[1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)},
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
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[0] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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}
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},
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[1] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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}
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},
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};
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#endif
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@@ -22,10 +22,10 @@ typedef enum periph_retention_module {
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* TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
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SLEEP_RETENTION_MODULE_SYS_PERIPH = 3,
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_TG0_WDT = 4,
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SLEEP_RETENTION_MODULE_TG0_WDT = 4,
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SLEEP_RETENTION_MODULE_TG1_WDT = 5,
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SLEEP_RETENTION_MODULE_TG0_TIMER = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER = 7,
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SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7,
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_GDMA_CH0 = 8,
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SLEEP_RETENTION_MODULE_GDMA_CH1 = 9,
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@@ -56,8 +56,8 @@ typedef enum periph_retention_module_bitmap {
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_BM_TASK_WDT = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
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SLEEP_RETENTION_MODULE_BM_INT_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER0),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER0),
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
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SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
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@@ -77,11 +77,11 @@ typedef enum periph_retention_module_bitmap {
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SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
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} periph_retention_module_bitmap_t;
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#define TOP_DOMAIN_PERIPHERALS_BM (SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
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#define TOP_DOMAIN_PERIPHERALS_BM (SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
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| SLEEP_RETENTION_MODULE_BM_TASK_WDT \
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| SLEEP_RETENTION_MODULE_BM_INT_WDT \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH1 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH2 \
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@@ -121,13 +121,19 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
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},
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};
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = {
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
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[0] = {
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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}
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},
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[1] = {
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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}
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},
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};
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@@ -24,8 +24,8 @@ typedef enum periph_retention_module {
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_TG0_WDT = 4,
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SLEEP_RETENTION_MODULE_TG1_WDT = 5,
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SLEEP_RETENTION_MODULE_TG0_TIMER = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER = 7,
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SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7,
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_GDMA_CH0 = 8,
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SLEEP_RETENTION_MODULE_GDMA_CH1 = 9,
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@@ -55,8 +55,8 @@ typedef enum periph_retention_module_bitmap {
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_BM_TASK_WDT = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
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SLEEP_RETENTION_MODULE_BM_INT_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER0),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER0),
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
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SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
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@@ -78,8 +78,8 @@ typedef enum periph_retention_module_bitmap {
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#define TOP_DOMAIN_PERIPHERALS_BM (SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
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| SLEEP_RETENTION_MODULE_BM_TASK_WDT \
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| SLEEP_RETENTION_MODULE_BM_INT_WDT \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH1 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH2 \
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@@ -121,13 +121,19 @@ const regdma_entries_config_t tg1_timer_regdma_entries[] = {
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},
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};
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = {
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
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[0] = {
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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}
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},
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[1] = {
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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}
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},
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};
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@@ -23,14 +23,16 @@ typedef enum periph_retention_module {
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_TG0_WDT = 3,
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SLEEP_RETENTION_MODULE_TG1_WDT = 4,
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SLEEP_RETENTION_MODULE_TG0_TIMER = 5,
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SLEEP_RETENTION_MODULE_TG1_TIMER = 6,
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SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5,
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SLEEP_RETENTION_MODULE_TG0_TIMER1 = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7,
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SLEEP_RETENTION_MODULE_TG1_TIMER1 = 8,
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/* MISC Peripherals */
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SLEEP_RETENTION_MODULE_UART0 = 7,
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SLEEP_RETENTION_MODULE_UART1 = 8,
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SLEEP_RETENTION_MODULE_UART2 = 9,
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SLEEP_RETENTION_MODULE_UART3 = 10,
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SLEEP_RETENTION_MODULE_UART4 = 11,
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SLEEP_RETENTION_MODULE_UART0 = 9,
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SLEEP_RETENTION_MODULE_UART1 = 10,
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SLEEP_RETENTION_MODULE_UART2 = 11,
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SLEEP_RETENTION_MODULE_UART3 = 12,
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SLEEP_RETENTION_MODULE_UART4 = 13,
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SLEEP_RETENTION_MODULE_MAX = 31
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} periph_retention_module_t;
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@@ -44,8 +46,10 @@ typedef enum periph_retention_module_bitmap {
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_BM_TG0_WDT = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
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SLEEP_RETENTION_MODULE_BM_TG1_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER0),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER1 = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER1),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER0),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER1 = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER1),
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/* MISC Peripherals */
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SLEEP_RETENTION_MODULE_BM_UART0 = BIT(SLEEP_RETENTION_MODULE_UART0),
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SLEEP_RETENTION_MODULE_BM_UART1 = BIT(SLEEP_RETENTION_MODULE_UART1),
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@@ -56,11 +60,13 @@ typedef enum periph_retention_module_bitmap {
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SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
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} periph_retention_module_bitmap_t;
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#define TOP_DOMAIN_PERIPHERALS_BM (SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
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#define TOP_DOMAIN_PERIPHERALS_BM (SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
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| SLEEP_RETENTION_MODULE_BM_TG0_WDT \
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| SLEEP_RETENTION_MODULE_BM_TG1_WDT \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER1 \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER1 \
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| SLEEP_RETENTION_MODULE_BM_UART0 \
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| SLEEP_RETENTION_MODULE_BM_UART1 \
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| SLEEP_RETENTION_MODULE_BM_UART2 \
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@@ -25,160 +25,210 @@ const timer_group_signal_conn_t timer_group_periph_signals = {
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}
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};
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/* Registers in retention context:
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* TIMG_T0CONFIG_REG / TIMG_T1CONFIG_REG
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* TIMG_T0ALARMLO_REG / TIMG_T1ALARMLO_REG
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* TIMG_T0ALARMHI_REG / TIMG_T1ALARMHI_REG
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* TIMG_T0LOADLO_REG / TIMG_T1LOADLO_REG
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* TIMG_T0LOADHI_REG / TIMG_T1LOADHI_REG
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* TIMG_T0CONFIG_REG
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* TIMG_T0ALARMLO_REG
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* TIMG_T0ALARMHI_REG
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* TIMG_T0LOADLO_REG
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* TIMG_T0LOADHI_REG
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* TIMG_INT_ENA_TIMERS_REG
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* TIMG_REGCLK_REG
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*/
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#define TG_TIMER_RETENTION_REGS_CNT 12
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static const uint32_t tg_timer_regs_map[4] = {0x1001e2f1, 0x80000000, 0x0, 0x0};
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#define TG0_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(0))
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#define TG1_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(1))
|
||||
#define TG_TIMER0_RETENTION_REGS_CNT 7
|
||||
static const uint32_t tg_timer0_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0};
|
||||
|
||||
const regdma_entries_config_t tg0_timer_regdma_entries[] = {
|
||||
/* Registers in retention context:
|
||||
* TIMG_T1CONFIG_REG
|
||||
* TIMG_T1ALARMLO_REG
|
||||
* TIMG_T1ALARMHI_REG
|
||||
* TIMG_T1LOADLO_REG
|
||||
* TIMG_T1LOADHI_REG
|
||||
* TIMG_INT_ENA_TIMERS_REG
|
||||
* TIMG_REGCLK_REG
|
||||
*/
|
||||
#define TG0_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(0) + 0x24)
|
||||
#define TG1_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(1) + 0x24)
|
||||
#define TG_TIMER1_RETENTION_REGS_CNT 7
|
||||
static const uint32_t tg_timer1_regs_map[4] = {0x800f1, 0x400000, 0x0, 0x0};
|
||||
|
||||
const regdma_entries_config_t tg0_timer0_regdma_entries[] = {
|
||||
// backup stage: trigger a soft capture
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00),
|
||||
TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x01),
|
||||
TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
|
||||
TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: wait for the capture done
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02),
|
||||
TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x03),
|
||||
TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1),
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01),
|
||||
TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save the captured counter value
|
||||
// restore stage: store the captured counter value to the loader register
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x04),
|
||||
TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[5] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x05),
|
||||
TIMG_T0HI_REG(0), TIMG_T0LOADHI_REG(0), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[6] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x06),
|
||||
TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[7] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07),
|
||||
TIMG_T1HI_REG(0), TIMG_T1LOADHI_REG(0), 2, 0, 0),
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02),
|
||||
TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
|
||||
[8] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08),
|
||||
TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[9] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x09),
|
||||
TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0),
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03),
|
||||
TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save other configuration and status registers
|
||||
// restore stage: restore the configuration and status registers
|
||||
[10] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x0a),
|
||||
TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0),
|
||||
TG_TIMER_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer_regs_map[0], tg_timer_regs_map[1],
|
||||
tg_timer_regs_map[2], tg_timer_regs_map[3]),
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04),
|
||||
TG0_TIMER0_RETENTION_REGS_BASE, TG0_TIMER0_RETENTION_REGS_BASE,
|
||||
TG_TIMER0_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer0_regs_map[0], tg_timer0_regs_map[1],
|
||||
tg_timer0_regs_map[2], tg_timer0_regs_map[3]),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
};
|
||||
|
||||
const regdma_entries_config_t tg1_timer_regdma_entries[] = {
|
||||
const regdma_entries_config_t tg0_timer1_regdma_entries[] = {
|
||||
// backup stage: trigger a soft capture
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05),
|
||||
TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: wait for the capture done
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x06),
|
||||
TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save the captured counter value
|
||||
// restore stage: store the captured counter value to the loader register
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07),
|
||||
TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08),
|
||||
TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save other configuration and status registers
|
||||
// restore stage: restore the configuration and status registers
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x09),
|
||||
TG0_TIMER1_RETENTION_REGS_BASE, TG0_TIMER1_RETENTION_REGS_BASE,
|
||||
TG_TIMER1_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer1_regs_map[0], tg_timer1_regs_map[1],
|
||||
tg_timer1_regs_map[2], tg_timer1_regs_map[3]),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
};
|
||||
|
||||
const regdma_entries_config_t tg1_timer0_regdma_entries[] = {
|
||||
// backup stage: trigger a soft capture
|
||||
[0] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00),
|
||||
TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x01),
|
||||
TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
|
||||
TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: wait for the capture done
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x02),
|
||||
TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x03),
|
||||
TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1),
|
||||
[1] = {
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01),
|
||||
TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save the captured counter value
|
||||
// restore stage: store the captured counter value to the loader register
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x04),
|
||||
TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[5] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x05),
|
||||
TIMG_T0HI_REG(1), TIMG_T0LOADHI_REG(1), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[6] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x06),
|
||||
TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[7] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07),
|
||||
TIMG_T1HI_REG(1), TIMG_T1LOADHI_REG(1), 2, 0, 0),
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02),
|
||||
TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
|
||||
[8] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08),
|
||||
TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
[9] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x09),
|
||||
TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0),
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03),
|
||||
TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save other configuration and status registers
|
||||
// restore stage: restore the configuration and status registers
|
||||
[10] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x0a),
|
||||
TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), TG_TIMER_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer_regs_map[0], tg_timer_regs_map[1],
|
||||
tg_timer_regs_map[2], tg_timer_regs_map[3]),
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04),
|
||||
TG1_TIMER0_RETENTION_REGS_BASE, TG1_TIMER0_RETENTION_REGS_BASE,
|
||||
TG_TIMER0_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer0_regs_map[0], tg_timer0_regs_map[1],
|
||||
tg_timer0_regs_map[2], tg_timer0_regs_map[3]),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
};
|
||||
|
||||
const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = {
|
||||
const regdma_entries_config_t tg1_timer1_regdma_entries[] = {
|
||||
// backup stage: trigger a soft capture
|
||||
[0] = {
|
||||
.regdma_entry_array = tg0_timer_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05),
|
||||
TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: wait for the capture done
|
||||
[1] = {
|
||||
.regdma_entry_array = tg1_timer_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
|
||||
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x06),
|
||||
TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save the captured counter value
|
||||
// restore stage: store the captured counter value to the loader register
|
||||
[2] = {
|
||||
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07),
|
||||
TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
|
||||
[3] = {
|
||||
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08),
|
||||
TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
// backup stage: save other configuration and status registers
|
||||
// restore stage: restore the configuration and status registers
|
||||
[4] = {
|
||||
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x09),
|
||||
TG1_TIMER1_RETENTION_REGS_BASE, TG1_TIMER1_RETENTION_REGS_BASE,
|
||||
TG_TIMER1_RETENTION_REGS_CNT, 0, 0,
|
||||
tg_timer1_regs_map[0], tg_timer1_regs_map[1],
|
||||
tg_timer1_regs_map[2], tg_timer1_regs_map[3]),
|
||||
.owner = ENTRY(0)
|
||||
},
|
||||
};
|
||||
|
||||
const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
|
||||
[0] = {
|
||||
[0] = {
|
||||
.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
|
||||
.regdma_entry_array = tg0_timer0_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg0_timer0_regdma_entries)
|
||||
},
|
||||
[1] = {
|
||||
.module = SLEEP_RETENTION_MODULE_TG0_TIMER1,
|
||||
.regdma_entry_array = tg0_timer1_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg0_timer1_regdma_entries)
|
||||
},
|
||||
},
|
||||
[1] = {
|
||||
[0] = {
|
||||
.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
|
||||
.regdma_entry_array = tg1_timer0_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg1_timer0_regdma_entries)
|
||||
},
|
||||
[1] = {
|
||||
.module = SLEEP_RETENTION_MODULE_TG1_TIMER1,
|
||||
.regdma_entry_array = tg1_timer1_regdma_entries,
|
||||
.array_size = ARRAY_SIZE(tg1_timer1_regdma_entries)
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
@@ -13,6 +13,10 @@
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/regdma.h"
|
||||
|
||||
#if SOC_TIMER_SUPPORT_SLEEP_RETENTION
|
||||
#include "soc/retention_periph_defs.h"
|
||||
#endif // SOC_TIMER_SUPPORT_SLEEP_RETENTION
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@@ -26,13 +30,14 @@ typedef struct {
|
||||
|
||||
extern const timer_group_signal_conn_t timer_group_periph_signals;
|
||||
|
||||
#if SOC_TIMER_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED
|
||||
#if SOC_TIMER_SUPPORT_SLEEP_RETENTION
|
||||
typedef struct {
|
||||
const periph_retention_module_t module;
|
||||
const regdma_entries_config_t *regdma_entry_array;
|
||||
uint32_t array_size;
|
||||
} tg_timer_reg_retention_info_t;
|
||||
|
||||
extern const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS];
|
||||
extern const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP];
|
||||
#endif // SOC_TIMER_SUPPORT_SLEEP_RETENTION
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
Reference in New Issue
Block a user