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Merge branch 'fix/rmii_ref_ckl_v5.4' into 'release/v5.4'

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fix(esp_eth): fixed ESP32P4 EMAC REF RMII CLK output mode (v5.4)

See merge request espressif/esp-idf!38039
This commit is contained in:
Jiang Jiang Jian
2025-04-07 13:58:48 +08:00
parent b809629dba ac29bd7ca4
commit 19e864060a
16 changed files with 149 additions and 42 deletions
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components/esp_hw_support/clk_ctrl_os.c
+23 -23
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -23,14 +23,14 @@ static const char *TAG = "clk_ctrl_os";
static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
static uint8_t s_periph_ref_counts = 0;
static uint32_t s_rc_fast_freq = 0; // Frequency of the RC_FAST clock in Hz
static uint32_t s_rc_fast_freq_hz = 0; // Frequency of the RC_FAST clock in Hz
#if SOC_CLK_APLL_SUPPORTED
// Current APLL frequency, in HZ. Zero if APLL is not enabled.
static uint32_t s_cur_apll_freq = 0;
static uint32_t s_cur_apll_freq_hz = 0;
static int s_apll_ref_cnt = 0;
#endif
#if SOC_CLK_MPLL_SUPPORTED
static uint32_t s_cur_mpll_freq = 0;
static uint32_t s_cur_mpll_freq_hz = 0;
static int s_mpll_ref_cnt = 0;
static esp_ldo_channel_handle_t s_ldo_chan = NULL;
#endif
@@ -41,8 +41,8 @@ bool periph_rtc_dig_clk8m_enable(void)
if (s_periph_ref_counts == 0) {
rtc_dig_clk8m_enable();
#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
s_rc_fast_freq = esp_clk_tree_rc_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT);
if (s_rc_fast_freq == 0) {
s_rc_fast_freq_hz = esp_clk_tree_rc_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT);
if (s_rc_fast_freq_hz == 0) {
rtc_dig_clk8m_disable();
portEXIT_CRITICAL(&periph_spinlock);
return false;
@@ -60,7 +60,7 @@ uint32_t periph_rtc_dig_clk8m_get_freq(void)
/* Workaround: CLK8M calibration cannot be performed, we can only return its theoretic value */
return SOC_CLK_RC_FAST_FREQ_APPROX;
#else
return s_rc_fast_freq;
return s_rc_fast_freq_hz;
#endif
}
@@ -70,7 +70,7 @@ void periph_rtc_dig_clk8m_disable(void)
assert(s_periph_ref_counts > 0);
s_periph_ref_counts--;
if (s_periph_ref_counts == 0) {
s_rc_fast_freq = 0;
s_rc_fast_freq_hz = 0;
rtc_dig_clk8m_disable();
}
portEXIT_CRITICAL(&periph_spinlock);
@@ -95,13 +95,13 @@ void periph_rtc_apll_release(void)
s_apll_ref_cnt--;
if (s_apll_ref_cnt == 0) {
// If there is no peripheral using APLL, shut down the power
s_cur_apll_freq = 0;
s_cur_apll_freq_hz = 0;
rtc_clk_apll_enable(false);
}
portEXIT_CRITICAL(&periph_spinlock);
}
esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq, uint32_t *real_freq)
esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz)
{
uint32_t o_div = 0;
uint32_t sdm0 = 0;
@@ -109,21 +109,21 @@ esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq, uint32_t *real_freq)
uint32_t sdm2 = 0;
// Guarantee 'periph_rtc_apll_acquire' has been called before set apll freq
assert(s_apll_ref_cnt > 0);
uint32_t apll_freq = rtc_clk_apll_coeff_calc(expt_freq, &o_div, &sdm0, &sdm1, &sdm2);
uint32_t apll_freq = rtc_clk_apll_coeff_calc(expt_freq_hz, &o_div, &sdm0, &sdm1, &sdm2);
ESP_RETURN_ON_FALSE(apll_freq, ESP_ERR_INVALID_ARG, TAG, "APLL coefficients calculate failed");
bool need_config = true;
portENTER_CRITICAL(&periph_spinlock);
/* If APLL is not in use or only one peripheral in use, its frequency can be changed as will
* But when more than one peripheral refers APLL, its frequency is not allowed to change once it is set */
if (s_cur_apll_freq == 0 || s_apll_ref_cnt < 2) {
s_cur_apll_freq = apll_freq;
if (s_cur_apll_freq_hz == 0 || s_apll_ref_cnt < 2) {
s_cur_apll_freq_hz = apll_freq;
} else {
apll_freq = s_cur_apll_freq;
apll_freq = s_cur_apll_freq_hz;
need_config = false;
}
portEXIT_CRITICAL(&periph_spinlock);
*real_freq = apll_freq;
*real_freq_hz = apll_freq;
if (need_config) {
ESP_LOGD(TAG, "APLL will working at %"PRIu32" Hz with coefficients [sdm0] %"PRIu32" [sdm1] %"PRIu32" [sdm2] %"PRIu32" [o_div] %"PRIu32"",
@@ -172,13 +172,13 @@ void periph_rtc_mpll_release(void)
s_mpll_ref_cnt--;
if (s_mpll_ref_cnt == 0) {
// If there is no peripheral using MPLL, shut down the power
s_cur_mpll_freq = 0;
s_cur_mpll_freq_hz = 0;
rtc_clk_mpll_disable();
}
portEXIT_CRITICAL(&periph_spinlock);
}
esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq, uint32_t *real_freq)
esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz)
{
esp_err_t ret = ESP_OK;
@@ -186,21 +186,21 @@ esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq, uint32_t *real_
assert(s_mpll_ref_cnt > 0);
portENTER_CRITICAL(&periph_spinlock);
if (s_cur_mpll_freq == expt_freq) {
if (s_cur_mpll_freq_hz == expt_freq_hz) {
goto end;
}
/* If MPLL is not in use or only one peripheral in use, its frequency can be changed as will
* But when more than one peripheral refers MPLL, its frequency is not allowed to change once it is set */
if (s_cur_mpll_freq == 0 || s_mpll_ref_cnt < 2) {
if (s_cur_mpll_freq_hz == 0 || s_mpll_ref_cnt < 2) {
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
rtc_clk_mpll_configure(xtal_freq_mhz, expt_freq / MHZ);
s_cur_mpll_freq = clk_ll_mpll_get_freq_mhz(xtal_freq_mhz);
rtc_clk_mpll_configure(xtal_freq_mhz, expt_freq_hz / MHZ);
s_cur_mpll_freq_hz = clk_ll_mpll_get_freq_mhz(xtal_freq_mhz) * MHZ;
} else {
ret = ESP_ERR_INVALID_STATE;
}
end:
if (real_freq != NULL) {
*real_freq = s_cur_mpll_freq;
if (real_freq_hz != NULL) {
*real_freq_hz = s_cur_mpll_freq_hz;
}
portEXIT_CRITICAL(&periph_spinlock);
return ret;
components/esp_hw_support/include/clk_ctrl_os.h
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -67,9 +67,9 @@ void periph_rtc_apll_release(void);
* @return
* - ESP_OK: APLL frequency set success
* - ESP_ERR_INVALID_ARG: The input expt_freq is out of APLL support range
* - ESP_ERR_INVALID_STATE: APLL is refered by more than one peripherals, not allowed to change its frequency now
* - ESP_ERR_INVALID_STATE: APLL is referred by more than one peripherals, not allowed to change its frequency now
*/
esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq, uint32_t *real_freq);
esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz);
#endif // SOC_CLK_APLL_SUPPORTED
#if SOC_CLK_MPLL_SUPPORTED
@@ -96,7 +96,7 @@ void periph_rtc_mpll_release(void);
* - ESP_OK: MPLL frequency set success
* - ESP_ERR_INVALID_STATE: MPLL is referred by more than one peripherals, not allowed to change its frequency now
*/
esp_err_t periph_rtc_mpll_freq_set(uint32_t expt_freq, uint32_t *real_freq);
esp_err_t periph_rtc_mpll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz);
#endif // SOC_CLK_MPLL_SUPPORTED
#ifdef __cplusplus
components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+3
View File
@@ -99,6 +99,9 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
case SOC_MOD_CLK_PLL_F25M:
clk_gate_ll_ref_25m_clk_en(enable);
break;
case SOC_MOD_CLK_PLL_F50M:
clk_gate_ll_ref_50m_clk_en(enable);
break;
case SOC_MOD_CLK_PLL_F80M:
clk_gate_ll_ref_80m_clk_en(enable);
break;