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refactor(hal): extract cache && mmu HAL into esp_hal_cache
This commit is contained in:
morris
@@ -0,0 +1,185 @@
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/*
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* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "hal/cache_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Cache hal config
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*/
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typedef struct {
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uint8_t core_nums; ///< CPU core numbers
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uint32_t l2_cache_size; ///< L2 cache size
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uint32_t l2_cache_line_size; ///< L2 cache line size
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} cache_hal_config_t;
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/**
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* Cache init and cache hal context init
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*
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* @param config Cache hal config
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*/
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void cache_hal_init(const cache_hal_config_t *config);
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/**
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* @brief Disable Cache
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*
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* Disable the ICache or DCache or both, of a certain level or all levels.
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* All the items in the corresponding Cache(s) will be invalideated.
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* Next request to these items will trigger a transaction to the physical memory
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*
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* @note If the autoload feature is enabled, this API will return until the ICache autoload is disabled.
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*/
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void cache_hal_disable(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Enable Cache
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*
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* Enable the ICache or DCache or both, of a certain level or all levels.
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*/
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void cache_hal_enable(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Suspend Cache
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*
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* Suspend the ICache or DCache or both, of a certain level or all levels.
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* This API suspends the CPU access to cache for a while, without invalidation.
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*/
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void cache_hal_suspend(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Resume Cache
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*
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* Resume the ICache or DCache or both, of a certain level or all levels.
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*/
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void cache_hal_resume(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Check if corresponding cache is enabled or not
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*
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* @return true: enabled; false: disabled
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*/
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bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Invalidate Cache supported addr
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*
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* Invalidate a Cache item for either ICache or DCache.
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*
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* @param vaddr Start address of the region to be invalidated
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* @param size Size of the region to be invalidated
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*
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* @return True for valid address. No operation if invalid
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*/
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bool cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size);
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#if SOC_CACHE_WRITEBACK_SUPPORTED
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/**
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* @brief Writeback Cache supported addr
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*
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* Writeback the DCache item to external memory
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*
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* @param vaddr Start address of the region to writeback
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* @param size Size of the region to writeback
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*
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* @return True for valid address. No operation if invalid
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*/
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bool cache_hal_writeback_addr(uint32_t vaddr, uint32_t size);
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#endif //#if SOC_CACHE_WRITEBACK_SUPPORTED
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#if SOC_CACHE_FREEZE_SUPPORTED
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/**
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* @brief Freeze Cache
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*
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* Freeze cache, CPU access to cache will be suspended, until the cache is unfrozen.
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*/
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void cache_hal_freeze(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Unfreeze cache
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*
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* Unfreeze cache, CPU access to cache will be restored
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*/
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void cache_hal_unfreeze(uint32_t cache_level, cache_type_t type);
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#endif //#if SOC_CACHE_FREEZE_SUPPORTED
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/**
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* @brief Get cache line size, in bytes
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*
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* @param cache_level Level of the Cache(s)
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* @param type see `cache_type_t`
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*
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* @return cache line size, in bytes. 0 stands for no such cache in this type or level
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*/
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uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Start cache preload for a region (manual preload)
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*
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* Preloads the given address range into cache, this can improve
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* performance when the region will be read soon.
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*
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* @param cache_level Level of the cache (e.g. CACHE_LL_LEVEL_EXT_MEM)
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* @param type CACHE_TYPE_DATA, CACHE_TYPE_INSTRUCTION, or CACHE_TYPE_ALL
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* @param vaddr Start virtual address of the region to preload
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* @param size Size in bytes. Should be cache-line aligned; if not,
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* the actual preloaded length is rounded down to cache-line boundary.
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* @param order preload order
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*/
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void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, cache_preload_order_t order);
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/**
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* @brief Wait until cache preload started by cache_hal_preload() is done
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*
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* @param cache_level Level of the cache (must match the level used in cache_hal_preload)
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* @param type CACHE_TYPE_DATA, CACHE_TYPE_INSTRUCTION, or CACHE_TYPE_ALL
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*/
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void cache_hal_preload_wait_done(uint32_t cache_level, cache_type_t type);
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/**
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* @brief Get Cache level and the ID of the vaddr
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*
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* @param vaddr_start virtual address start
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* @param len vaddr length
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* @param out_level cache level
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* @param out_id cache id
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*
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* @return true for valid, false for invalid addr or null pointer
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*/
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bool cache_hal_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,38 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "hal/cache_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_CACHE_CNT_SUPPORTED
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/**
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* @brief Description of one cache profile counter unit
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*
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* A unit is one set of counters observing one traffic stream, e.g. the
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* instruction fetches of core 0 into the L1 cache.
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*/
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typedef struct {
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const char *name; /*!< Short human-readable name */
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uint8_t level; /*!< Cache level (1 or 2) */
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cache_profile_traffic_t traffic; /*!< Kind of traffic observed */
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int8_t core_id; /*!< Originating core, -1 if unknown/mixed */
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uint32_t counter_reg[CACHE_PROFILE_COUNTER_MAX]; /*!< Counter registers; 0 if the unit
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does not have that counter */
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} cache_profile_counter_unit_t;
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extern const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM];
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#endif
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,69 @@
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/*
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* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Kind of traffic observed by a cache profile counter unit
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*/
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typedef enum {
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CACHE_PROFILE_TRAFFIC_INST, /*!< Instruction fetches */
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CACHE_PROFILE_TRAFFIC_DATA, /*!< Data accesses */
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CACHE_PROFILE_TRAFFIC_UNIFIED, /*!< Mixed/unknown (unified request bus) */
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} cache_profile_traffic_t;
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/**
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* @brief One of the counters of a cache profile counter unit
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*/
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typedef enum {
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CACHE_PROFILE_COUNTER_HIT, /*!< Completed accesses ("hit" counter) */
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CACHE_PROFILE_COUNTER_MISS, /*!< Miss stall events ("miss" counter) */
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CACHE_PROFILE_COUNTER_CONFLICT, /*!< Requester conflicts */
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CACHE_PROFILE_COUNTER_NXTLVL_RD, /*!< Line fills from the next level */
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CACHE_PROFILE_COUNTER_NXTLVL_WR, /*!< Write-backs to the next level */
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CACHE_PROFILE_COUNTER_MAX,
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} cache_profile_counter_t;
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typedef enum {
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CACHE_TYPE_DATA,
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CACHE_TYPE_INSTRUCTION,
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CACHE_TYPE_ALL //This means both ICache and DCache will be used. On some chips, I/D are controlled by a shared Cache. Also use this enum under this condition. See `SOC_SHARED_IDCACHE_SUPPORTED`.
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} cache_type_t;
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/**
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* @brief Ibuses and Dbuses.
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*
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* @note
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* These enumurations are abstract concepts. Virtual address reside in one of these buses.
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* Therefore, use `cache_ll_l1_get_bus(bus_id, vaddr_start, len)` to convert your vaddr into buses first
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*/
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typedef enum {
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CACHE_BUS_IBUS0 = BIT(0),
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CACHE_BUS_IBUS1 = BIT(1),
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CACHE_BUS_IBUS2 = BIT(2),
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CACHE_BUS_DBUS0 = BIT(3),
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CACHE_BUS_DBUS1 = BIT(4),
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CACHE_BUS_DBUS2 = BIT(5),
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} cache_bus_mask_t;
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/**
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* @brief Preload order
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*/
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typedef enum {
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CACHE_PRELOAD_ORDER_ASCENDING,
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CACHE_PRELOAD_ORDER_DESCENDING,
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} cache_preload_order_t;
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,187 @@
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/*
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* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <esp_types.h>
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#include "soc/soc_caps.h"
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#include "hal/mmu_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief MMU hal config
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*/
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typedef struct {
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uint8_t core_nums; ///< CPU core numbers
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uint32_t mmu_page_size; ///< MMU page size
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} mmu_hal_config_t;
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/**
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* MMU Hal layer initialisation
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*
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* @param config MMU hal config
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*/
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void mmu_hal_init(const mmu_hal_config_t *config);
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/**
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* MMU Hal layer context initialisation
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*
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* @param config MMU hal config
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*/
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void mmu_hal_ctx_init(const mmu_hal_config_t *config);
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/**
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* Unmap all the MMU table. After this all external memory vaddr are not available
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*/
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void mmu_hal_unmap_all(void);
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/**
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* Helper functions to convert the MMU page numbers into bytes. e.g.:
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* - When MMU page size is 16KB, page_num = 2 will be converted into 32KB
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* - When MMU page size is 32KB, page_num = 2 will be converted into 64KB
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*
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* @param mmu_id MMU ID
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* @param page_num page numbers
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*
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* @return
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* length in byte
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*/
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uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num);
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/**
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* Helper functions to convert bytes into MMU page numbers. e.g.:
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* - When MMU page size is 16KB, bytes = 64KB will be converted into 4 pages
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* - When MMU page size is 32KB, bytes = 64KB will be converted into 2 pages
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*
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* @param mmu_id MMU ID
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* @param bytes length in byte
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*
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* @return
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* length in CONFIG_MMU_PAGE_SIZE
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*/
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uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes);
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/**
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* To map a virtual address block to a physical memory block
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*
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* @param mmu_id MMU ID
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* @param mem_type physical memory type, see `mmu_target_t`
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* @param vaddr start virtual address to be mapped
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* @param paddr start physical address to be mapped
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* @param len length to be mapped, in bytes
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* @param[out] out_len actual mapped length
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*
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* @note vaddr and paddr should be aligned with the mmu page size, see CONFIG_MMU_PAGE_SIZE
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*/
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void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len);
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#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE
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/**
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* Map a PSRAM physical range to virtual memory without setting the encryption
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* SENSITIVE bit on each MMU entry. Used only for the explicitly carved-out
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* unencrypted PSRAM region (see CONFIG_SPIRAM_ENC_EXEMPT).
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*
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* @param vaddr start virtual address (MMU-page-aligned)
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* @param paddr start physical address (MMU-page-aligned)
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* @param len length in bytes
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*/
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void mmu_hal_map_region_no_enc(uint32_t vaddr, uint32_t paddr, uint32_t len);
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#endif
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/**
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* To unmap a virtual address block that is mapped to a physical memory block previously
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*
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* @param[in] mmu_id MMU ID
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* @param[in] vaddr start virtual address
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* @param[in] len length to be unmapped, in bytes
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*/
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void mmu_hal_unmap_region(uint32_t mmu_id, uint32_t vaddr, uint32_t len);
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/**
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* Convert virtual address to physical address
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*
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* @param mmu_id MMU ID
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* @param vaddr virtual address
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* @param[out] out_paddr physical address
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* @param[out] out_target Indicating the vaddr/paddr is mapped on which target, see `mmu_target_t`
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*
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* @return
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* - true: virtual address is valid
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* - false: virtual address isn't valid
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*/
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bool mmu_hal_vaddr_to_paddr(uint32_t mmu_id, uint32_t vaddr, uint32_t *out_paddr, mmu_target_t *out_target);
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/**
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* Convert physical address to virtual address
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*
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* @note This function can only find the first match virtual address.
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* However it is possible that a physical address is mapped to multiple virtual addresses.
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*
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* @param mmu_id MMU ID
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* @param paddr physical address
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* @param target physical memory target, see `mmu_target_t`
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* @param type virtual address type, could be instruction or data
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* @param[out] out_vaddr virtual address
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*
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* @return
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* - true: found a matched vaddr
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* - false: not found a matched vaddr
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*/
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bool mmu_hal_paddr_to_vaddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target, mmu_vaddr_t type, uint32_t *out_vaddr);
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/**
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* Check if the vaddr region is valid
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*
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* @param mmu_id MMU ID
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* @param vaddr_start start of the virtual address
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* @param len length, in bytes
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* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
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*
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* @return
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* True for valid
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*/
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bool mmu_hal_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type);
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/**
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* Check if the paddr region is valid
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*
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* @param mmu_id MMU ID
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* @param paddr_start start of the physical address
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* @param len length, in bytes
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*
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* @return
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* True for valid
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*/
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bool mmu_hal_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len);
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#if SOC_MMU_PER_EXT_MEM_TARGET
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/**
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* Get MMU ID from MMU target
|
||||
*
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* @param target MMU target
|
||||
*
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||||
* @return
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||||
* MMU ID
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||||
*/
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||||
uint32_t mmu_hal_get_id_from_target(mmu_target_t target);
|
||||
|
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/**
|
||||
* Get MMU ID from vaddr
|
||||
*
|
||||
* @param vaddr Virtual address
|
||||
*
|
||||
* @return
|
||||
* MMU ID
|
||||
*/
|
||||
uint32_t mmu_hal_get_id_from_vaddr(uint32_t vaddr);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
MMU_MEM_CAP_EXEC = BIT(0),
|
||||
MMU_MEM_CAP_READ = BIT(1),
|
||||
MMU_MEM_CAP_WRITE = BIT(2),
|
||||
MMU_MEM_CAP_32BIT = BIT(3),
|
||||
MMU_MEM_CAP_8BIT = BIT(4),
|
||||
} mmu_mem_caps_t;
|
||||
|
||||
/**
|
||||
* MMU Page size
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_PAGE_8KB = 0x2000,
|
||||
MMU_PAGE_SIZE_MIN = MMU_PAGE_8KB,
|
||||
MMU_PAGE_16KB = 0x4000,
|
||||
MMU_PAGE_32KB = 0x8000,
|
||||
MMU_PAGE_64KB = 0x10000,
|
||||
MMU_PAGE_128KB = 0x20000,
|
||||
MMU_PAGE_256KB = 0x40000,
|
||||
MMU_PAGE_SIZE_MAX = MMU_PAGE_256KB,
|
||||
} mmu_page_size_t;
|
||||
|
||||
/**
|
||||
* MMU virtual address flags type
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_VADDR_DATA = BIT(0),
|
||||
MMU_VADDR_INSTRUCTION = BIT(1),
|
||||
} mmu_vaddr_t;
|
||||
|
||||
/**
|
||||
* External physical memory
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_TARGET_FLASH0 = BIT(0),
|
||||
MMU_TARGET_PSRAM0 = BIT(1),
|
||||
} mmu_target_t;
|
||||
|
||||
/**
|
||||
* MMU table id
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_TABLE_CORE0,
|
||||
MMU_TABLE_CORE1,
|
||||
} mmu_table_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user