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refactor(hal): extract cache && mmu HAL into esp_hal_cache
This commit is contained in:
morris
@@ -0,0 +1,678 @@
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/*
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32s2/rom/cache.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
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#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
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#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
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#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
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#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
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#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
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#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
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#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
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#define CACHE_LL_L1_DCACHE_AUTOLOAD (1<<0)
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/**
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* @brief Preload strategy
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*/
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typedef enum {
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CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
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CACHE_LL_PRELOAD_AFTER_FETCH = 1,
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CACHE_LL_PRELOAD_ARBITRARY = 2,
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} cache_ll_preload_strategy_t;
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/**
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* @brief Initialize the cache clock
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*/
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__attribute__((always_inline))
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static inline void cache_ll_clk_init(void)
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{
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//for compatibility
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}
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/**
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* @brief Check if ICache auto preload is enabled or not
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_icache_autoload_enabled(void)
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{
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bool enabled = false;
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if (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_AUTOLOAD_ENA)) {
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enabled = true;
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}
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return enabled;
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}
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/**
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* @brief Check if DCache auto preload is enabled or not
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_dcache_autoload_enabled(void)
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{
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bool enabled = false;
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if (REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_AUTOLOAD_ENA)) {
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enabled = true;
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}
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return enabled;
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}
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/**
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* @brief Check if Cache auto preload is enabled or not.
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled = false;
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switch (type) {
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case CACHE_TYPE_INSTRUCTION:
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enabled = cache_ll_l1_is_icache_autoload_enabled();
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break;
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case CACHE_TYPE_DATA:
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enabled = cache_ll_l1_is_dcache_autoload_enabled();
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break;
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default: //CACHE_TYPE_ALL
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enabled = cache_ll_l1_is_icache_autoload_enabled() && cache_ll_l1_is_dcache_autoload_enabled();
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break;
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}
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return enabled;
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}
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/**
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* @brief Set the preload strategy (no-op)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
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{
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(void)cache_level;
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(void)type;
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(void)cache_id;
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(void)strategy;
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}
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/**
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* @brief Preload cache
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*
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* @param cache_level level of the cache (must be CACHE_LL_LEVEL_EXT_MEM)
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* @param type see `cache_type_t` (INSTRUCTION, DATA, or ALL)
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* @param cache_id id of the cache (unused on S2; pass 0 or CACHE_LL_ID_ALL)
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* @param vaddr start virtual address of the preload region
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* @param size size of the preload region in bytes
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* @param order preload order, see `cache_preload_order_t`
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*/
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__attribute__((always_inline))
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static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
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{
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(void)cache_id;
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HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
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switch (type) {
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case CACHE_TYPE_INSTRUCTION:
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Cache_Start_ICache_Preload(vaddr, size, order);
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break;
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case CACHE_TYPE_DATA:
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Cache_Start_DCache_Preload(vaddr, size, order);
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break;
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case CACHE_TYPE_ALL:
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default:
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Cache_Start_ICache_Preload(vaddr, size, order);
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Cache_Start_DCache_Preload(vaddr, size, order);
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break;
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}
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}
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/**
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* @brief Wait until cache preload is done (L1 only)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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(void)cache_id;
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HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
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switch (type) {
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case CACHE_TYPE_INSTRUCTION:
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while (Cache_ICache_Preload_Done() == 0) {
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}
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break;
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case CACHE_TYPE_DATA:
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while (Cache_DCache_Preload_Done() == 0) {
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}
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break;
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case CACHE_TYPE_ALL:
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default:
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while (Cache_ICache_Preload_Done() == 0) {
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}
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while (Cache_DCache_Preload_Done() == 0) {
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}
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break;
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}
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}
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/**
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* @brief Disable ICache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_icache(void)
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{
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Cache_Disable_ICache();
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}
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/**
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* @brief Disable DCache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_dcache(void)
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{
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Cache_Disable_DCache();
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}
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/**
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* @brief Disable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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switch (type) {
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_disable_icache();
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_disable_dcache();
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_disable_icache();
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cache_ll_l1_disable_dcache();
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break;
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}
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}
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/**
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* @brief Enable ICache
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*
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* @param inst_autoload_en ICache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_enable_icache(bool inst_autoload_en)
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{
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Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Enable DCache
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*
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* @param data_autoload_en DCache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_enable_dcache(bool data_autoload_en)
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{
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Cache_Enable_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Enable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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switch (type) {
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_enable_icache(inst_autoload_en);
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_enable_dcache(data_autoload_en);
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_enable_icache(inst_autoload_en);
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cache_ll_l1_enable_dcache(data_autoload_en);
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break;
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}
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}
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/**
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* @brief Suspend ICache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_suspend_icache(void)
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{
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Cache_Suspend_ICache();
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}
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/**
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* @brief Suspend DCache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_suspend_dcache(void)
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{
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Cache_Suspend_DCache();
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}
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/**
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* @brief Suspend Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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switch (type) {
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_suspend_icache();
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_suspend_dcache();
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_suspend_icache();
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cache_ll_l1_suspend_dcache();
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break;
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}
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}
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/**
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* @brief Resume ICache
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*
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* @param inst_autoload_en ICache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_resume_icache(bool inst_autoload_en)
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{
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Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Resume DCache
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*
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* @param data_autoload_en DCache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_resume_dcache(bool data_autoload_en)
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{
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Cache_Resume_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Resume Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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switch (type) {
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_resume_icache(inst_autoload_en);
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_resume_dcache(data_autoload_en);
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_resume_icache(inst_autoload_en);
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cache_ll_l1_resume_dcache(data_autoload_en);
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break;
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}
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}
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/**
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* @brief Check if ICache is enabled or not
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled;
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enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE);
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return enabled;
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}
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/**
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* @brief Check if DCache is enabled or not
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_dcache_enabled(uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled;
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enabled = REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE);
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return enabled;
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}
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|
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/**
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* @brief Check if ICache or DCache or both is enabled or not
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*
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||||
* @param type see `cache_type_t`
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_enabled(cache_type_t type)
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{
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||||
bool enabled = false;
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switch (type) {
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case CACHE_TYPE_DATA:
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enabled = cache_ll_l1_is_dcache_enabled(0);
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break;
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||||
case CACHE_TYPE_INSTRUCTION:
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enabled = cache_ll_l1_is_icache_enabled(0);
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||||
break;
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||||
default: //CACHE_TYPE_ALL
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||||
enabled = cache_ll_l1_is_dcache_enabled(0) && cache_ll_l1_is_icache_enabled(0);
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break;
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}
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return enabled;
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||||
}
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||||
|
||||
/**
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||||
* @brief Invalidate cache supported addr
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*
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* Invalidate a cache item
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*
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* @param cache_level level of the cache
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||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
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||||
* @param vaddr start address of the region to be invalidated
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||||
* @param size size of the region to be invalidated
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||||
*/
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__attribute__((always_inline))
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static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
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||||
{
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Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
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||||
*
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||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
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||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
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||||
switch (type) {
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||||
case CACHE_TYPE_DATA:
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||||
Cache_Invalidate_DCache_All();
|
||||
break;
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
Cache_Invalidate_ICache_All();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
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||||
Cache_Invalidate_ICache_All();
|
||||
Cache_Invalidate_DCache_All();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writeback cache supported addr
|
||||
*
|
||||
* Writeback a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be written back
|
||||
* @param size size of the region to be written back
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_WriteBack_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ICache line size, in bytes
|
||||
*
|
||||
* @return ICache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_l1_icache_get_line_size(void)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DCache line size, in bytes
|
||||
*
|
||||
* @return DCache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_l1_dcache_get_line_size(void)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_DCache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
size = cache_ll_l1_icache_get_line_size();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
size = cache_ll_l1_dcache_get_line_size();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
|
||||
} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DRAM1_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS2);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DROM0_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
(void)bus_id;
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
|
||||
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
|
||||
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
(void)bus_id;
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
|
||||
REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
|
||||
REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= ((vaddr_start >= SOC_DROM0_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH));
|
||||
valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM1_ADDRESS_HIGH));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get cache debug status 0
|
||||
*
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_dbg_status0(void)
|
||||
{
|
||||
return REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get cache debug status 1
|
||||
*
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_dbg_status1(void)
|
||||
{
|
||||
return REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,384 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - 0x10000)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (192 - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (vaddr_type == MMU_VADDR_DATA) {
|
||||
vaddr_base = SOC_MMU_DBUS_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_IBUS_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
//On esp32s2, MMU Page size is always 64KB
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*
|
||||
* @note On esp32s2, only supports `MMU_PAGE_64KB`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
HAL_ASSERT(size == MMU_PAGE_64KB);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
bool valid = false;
|
||||
|
||||
if (type & MMU_VADDR_DATA) {
|
||||
valid |= ((vaddr_start >= SOC_DROM0_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH));
|
||||
}
|
||||
|
||||
if (type & MMU_VADDR_INSTRUCTION) {
|
||||
valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM1_ADDRESS_HIGH));
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t offset = 0;
|
||||
|
||||
if (SOC_ADDRESS_IN_DROM0(vaddr)) {
|
||||
offset = PRO_CACHE_IBUS2_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)) {
|
||||
offset = PRO_CACHE_IBUS0_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_IRAM1(vaddr)) {
|
||||
offset = PRO_CACHE_IBUS1_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_DPORT_CACHE(vaddr)) {
|
||||
offset = PRO_CACHE_DBUS2_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_DRAM1(vaddr)) {
|
||||
offset = PRO_CACHE_DBUS1_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)) {
|
||||
offset = PRO_CACHE_DBUS0_MMU_START / 4;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return offset + ((vaddr & SOC_MMU_VADDR_MASK) >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
return paddr >> 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
uint32_t target_code = (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | SOC_MMU_VALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id));
|
||||
|
||||
if ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_ACCESS_FLASH) {
|
||||
return MMU_TARGET_FLASH0;
|
||||
} else {
|
||||
return MMU_TARGET_PSRAM0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
|
||||
uint32_t vaddr_base = 0;
|
||||
if (entry_id < 0x40) {
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 0x40 && entry_id < 0x80) {
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x40;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 0x80 && entry_id < 0xC0) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x80;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else if (entry_id >= 0xC0 && entry_id < 0x100) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0xC0;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else if (entry_id >= 0x100 && entry_id < 0x140) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x100;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else if (entry_id >= 0x140 && entry_id < 0x180) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x140;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return vaddr_base + (entry_id << 16);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user