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https://github.com/espressif/esp-idf.git
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refactor(hal): extract cache && mmu HAL into esp_hal_cache
This commit is contained in:
morris
@@ -0,0 +1,472 @@
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/*
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/cache_reg.h"
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#include "soc/cache_struct.h"
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#include "soc/ext_mem_defs.h"
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#include "rom/cache.h"
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#include "hal/cache_periph.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32c5/rom/cache.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
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#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
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#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
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#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
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#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
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#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
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#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
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#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
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#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
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#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f)
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/**
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* @brief Preload strategy
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*/
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typedef enum {
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CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
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CACHE_LL_PRELOAD_AFTER_FETCH = 1,
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CACHE_LL_PRELOAD_ARBITRARY = 2,
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} cache_ll_preload_strategy_t;
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/**
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* @brief Initialize the cache clock
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*/
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__attribute__((always_inline))
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static inline void cache_ll_clk_init(void)
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{
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//for compatibility
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}
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/**
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* @brief Check if Cache auto preload is enabled or not.
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled = false;
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if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
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enabled = true;
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}
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return enabled;
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}
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/**
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* @brief Disable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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(void) type;
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Cache_Disable_Cache();
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}
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/**
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* @brief Enable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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Cache_Enable_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Suspend Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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Cache_Suspend_Cache();
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}
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/**
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* @brief Resume Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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Cache_Resume_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Invalidate cache supported addr
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*
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* Invalidate a cache item
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param vaddr start address of the region to be invalidated
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* @param size size of the region to be invalidated
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*/
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__attribute__((always_inline))
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static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
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{
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Cache_Invalidate_Addr(vaddr, size);
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}
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/**
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* @brief Invalidate all
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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Cache_Invalidate_All();
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}
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/**
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* @brief Writeback cache supported addr
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*
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* Writeback a cache item
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param vaddr start address of the region to be written back
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* @param size size of the region to be written back
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*/
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__attribute__((always_inline))
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static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
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{
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Cache_WriteBack_Addr(vaddr, size);
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}
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/**
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* @brief Freeze Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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Cache_Freeze_Enable(CACHE_FREEZE_ACK_BUSY);
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}
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/**
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* @brief Unfreeze Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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Cache_Freeze_Disable();
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}
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/**
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* @brief Set the preload strategy (L1 unified)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
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{
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(void)cache_id;
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(void)type;
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if (cache_level == CACHE_LL_LEVEL_EXT_MEM || cache_level == CACHE_LL_LEVEL_ALL) {
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CACHE.l1_icache_ctrl.l1_icache_undef_op = strategy;
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}
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}
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/**
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* @brief Preload cache (L1 unified)
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*
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* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
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*
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* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
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* @param type see `cache_type_t`
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* @param cache_id id of the cache (unused; pass 0)
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* @param vaddr start virtual address of the preload region
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* @param size size of the preload region in bytes
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* @param order preload order, see `cache_preload_order_t`
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*/
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__attribute__((always_inline))
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static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
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{
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(void)cache_id;
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(void)type;
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HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
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Cache_Start_Preload(vaddr, size, order);
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}
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/**
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* @brief Wait until cache preload is done (L1 only)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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(void)cache_id;
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(void)type;
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HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
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while (Cache_Preload_Done() == 0) {
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}
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}
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/**
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* @brief Get Cache line size, in bytes
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*
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* @return Cache line size, in bytes
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*/
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__attribute__((always_inline))
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static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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uint32_t size = 0;
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size = Cache_Get_Line_Size(CACHE_MAP_FLASH_CACHE);
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return size;
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}
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/**
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* @brief Get the buses of a particular cache that are mapped to a virtual address range
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*
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* External virtual address can only be accessed when the involved cache buses are enabled.
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* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param vaddr_start virtual address start
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* @param len vaddr length
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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cache_bus_mask_t mask = (cache_bus_mask_t)0;
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uint32_t vaddr_end = vaddr_start + len - 1;
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if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
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//c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
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mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
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} else {
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HAL_ASSERT(0); //Out of region
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}
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return mask;
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}
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/**
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* Enable the Cache Buses
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*
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* @param bus_id bus ID
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* @param mask To know which buses should be enabled
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
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{
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//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
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REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
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REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
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}
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/**
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* Disable the Cache Buses
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*
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* @param bus_id bus ID
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* @param mask To know which buses should be disabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
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{
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//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
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REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
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REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
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}
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/**
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* @brief Get Cache level and the ID of the vaddr
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*
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* @param vaddr_start virtual address start
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* @param len vaddr length
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* @param out_level cache level
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* @param out_id cache id
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*
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* @return true for valid
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
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{
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bool valid = false;
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uint32_t vaddr_end = vaddr_start + len - 1;
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valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
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valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
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if (valid) {
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*out_level = 1;
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*out_id = 0;
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}
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return valid;
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}
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/**
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* Enable the Cache fail tracer
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*
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* @param cache_id cache ID
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* @param en enable / disable
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*/
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static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
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{
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CACHE.trace_ena.l1_cache_trace_ena = en;
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}
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/*------------------------------------------------------------------------------
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* Interrupt
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*----------------------------------------------------------------------------*/
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/**
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* @brief Enable Cache access error interrupt
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*
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* @param cache_id Cache ID
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
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{
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CACHE.l1_cache_acs_fail_int_ena.val |= mask;
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}
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/**
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* @brief Clear Cache access error interrupt status
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*
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* @param cache_id Cache ID
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
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{
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CACHE.l1_cache_acs_fail_int_clr.val = mask;
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}
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/**
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* @brief Get Cache access error interrupt status
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*
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* @param cache_id Cache ID
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* @param mask Interrupt mask
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*
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* @return Status mask
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*/
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static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
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{
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return CACHE.l1_cache_acs_fail_int_st.val & mask;
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}
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/*----------------------------------------------------------------------------
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Cache Profile Counter Related
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-----------------------------------------------------------------------------*/
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#define CACHE_LL_PROFILE_CNT_ENA_MASK (CACHE_L1_BUS0_CNT_ENA | CACHE_L1_BUS1_CNT_ENA)
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#define CACHE_LL_PROFILE_CNT_CLR_MASK (CACHE_L1_BUS0_CNT_CLR | CACHE_L1_BUS1_CNT_CLR)
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/**
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* @brief Enable or disable the cache profile counters
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||||
*
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||||
* @param ena True to enable, false to disable
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*/
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||||
__attribute__((always_inline))
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static inline void cache_ll_enable_profile_counter(bool ena)
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{
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if (ena) {
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REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
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||||
} else {
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||||
REG_CLR_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
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||||
}
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||||
}
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||||
|
||||
/**
|
||||
* @brief Reset all cache profile counters to zero
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clear_profile_counter(void)
|
||||
{
|
||||
/* clear bits are write-to-trigger and self-clearing */
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_CLR_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one counter of a cache profile counter unit
|
||||
*
|
||||
* @param unit Unit index, 0 to SOC_CACHE_CNT_UNITS_NUM - 1
|
||||
* @param counter Counter to read
|
||||
* @param[out] value Counter value, only written if the counter exists
|
||||
*
|
||||
* @return True if the unit has this counter, false otherwise
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_get_profile_counter(int unit, cache_profile_counter_t counter, uint32_t *value)
|
||||
{
|
||||
HAL_ASSERT(unit < SOC_CACHE_CNT_UNITS_NUM);
|
||||
uint32_t reg = cache_periph_profile_counter_units[unit].counter_reg[counter];
|
||||
if (reg == 0) {
|
||||
return false;
|
||||
}
|
||||
*value = REG_READ(reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,437 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "esp_fault.h"
|
||||
#if SOC_EFUSE_SUPPORTED
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_FLASH_MMU_ID 0
|
||||
#define MMU_LL_PSRAM_MMU_ID 0
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
(void)vaddr_type;
|
||||
//On ESP32C5, I/D share the same vaddr range
|
||||
return SOC_MMU_IBUS_VADDR_BASE | laddr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
#if SOC_EFUSE_SUPPORTED
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
HAL_ASSERT(size == MMU_PAGE_64KB);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
// For PSRAM case, avoid encryption due to a bug in the hardware
|
||||
if (!(target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() <= 100)) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
}
|
||||
mmu_val |= (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
|
||||
mmu_raw_value = mmu_val | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
|
||||
#if !BOOTLOADER_BUILD && !ESP_TEE_BUILD
|
||||
// Anti-FI check to confirm the encryption status for PSRAM entry.
|
||||
// This avoids a potential FI attacks to keep PSRAM unencrypted and
|
||||
// hence read out plaintext in execute from PSRAM model.
|
||||
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
|
||||
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
|
||||
} else {
|
||||
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100));
|
||||
}
|
||||
#endif // !BOOTLOADER_BUILD && !ESP_TEE_BUILD
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a PSRAM MMU entry without the SENSITIVE bit, used only for the
|
||||
* carved-out unencrypted region (see CONFIG_SPIRAM_ENC_EXEMPT).
|
||||
*
|
||||
* No anti-FI check: the SENSITIVE bit is intentionally clear, and an FI flip
|
||||
* that sets it would force decryption of plaintext data (garbage, fails safe).
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry_no_enc(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value = mmu_val | SOC_MMU_ACCESS_SPIRAM | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
|
||||
}
|
||||
if (!(mmu_raw_value & SOC_MMU_VALID)) {
|
||||
return 0;
|
||||
}
|
||||
ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_target_t target = ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_ACCESS_SPIRAM) == 0) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0;
|
||||
return target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
|
||||
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user