refactor(hal): extract cache && mmu HAL into esp_hal_cache

components/esp_hal_cache/esp32c5/cache_periph.c

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/cache_reg.h"
+#include "hal/cache_periph.h"
+
+/*
+ * ESP32-C5 cache profile counter units.
+ *
+ * Single cache level shared by instructions and data (the flash/PSRAM
+ * cache, 32-byte lines), with two request buses: bus0 carries instruction
+ * fetches, bus1 carries data accesses. Counter semantics match the
+ * ESP32-P4. The hit/miss/conflict counters use the BUS0/BUS1 register
+ * names while the corresponding next-level counters use the DBUS0/DBUS1
+ * names. Only the CPU request buses are exposed here.
+ */
+
+const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
+    {
+        .name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
+        .counter_reg = {
+            [CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
+            [CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
+            [CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
+            [CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
+        },
+    },
+    {
+        .name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
+        .counter_reg = {
+            [CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
+            [CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
+            [CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
+            [CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
+            [CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
+        },
+    },
+};