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refactor(hal): extract cache && mmu HAL into esp_hal_cache
This commit is contained in:
morris
@@ -0,0 +1,258 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/dport_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CACHE_LL_ID_ALL 2 //All of the caches in a type and level, make this value greater than any ID
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#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
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#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
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#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
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#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
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/**
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* @brief enable a cache unit
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_enable_cache(uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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if (cache_id == 0) {
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DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
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} else {
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
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}
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}
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/**
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* @brief disable a cache unit
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_cache(uint32_t cache_id)
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{
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if (cache_id == 0) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
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;
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}
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
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} else {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
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;
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}
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
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}
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}
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/**
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* @brief Get the status of cache if it is enabled or not
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param type see `cache_type_t`
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* @return enabled or not
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_cache_enabled(uint32_t cache_id, cache_type_t type)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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(void) type; //On 32 it shares between I and D cache
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bool enabled;
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if (cache_id == 0) {
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enabled = DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
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} else {
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enabled = DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
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}
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return enabled;
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}
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/**
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* @brief Get the buses of a particular cache that are mapped to a virtual address range
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*
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* External virtual address can only be accessed when the involved cache buses are enabled.
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* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param vaddr_start virtual address start
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* @param len vaddr length
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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cache_bus_mask_t mask = (cache_bus_mask_t)0;
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uint32_t vaddr_end = vaddr_start + len - 1;
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if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_HIGH) {
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HAL_ASSERT(false); //out of range
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} else if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
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} else if (vaddr_start >= SOC_IRAM1_CACHE_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));
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} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));
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} else if (vaddr_start >= SOC_DRAM1_CACHE_ADDRESS_LOW) {
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HAL_ASSERT(vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
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} else if (vaddr_start >= SOC_DROM0_CACHE_ADDRESS_LOW) {
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HAL_ASSERT(vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
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} else {
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HAL_ASSERT(false);
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}
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return mask;
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}
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/**
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* Enable the Cache Buses
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*
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* @param bus_id bus ID
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
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{
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(void) mask;
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uint32_t bus_mask = 0;
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if (bus_id == 0) {
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0);
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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/**
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* Returns enabled buses for a given core
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return State of enabled buses
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*/
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__attribute__((always_inline))
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static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
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{
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cache_bus_mask_t mask = (cache_bus_mask_t)0;
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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if (cache_id == 0) {
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uint32_t bus_mask = DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG);
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));
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} else {
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uint32_t bus_mask = DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG);
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));
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}
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return mask;
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}
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/**
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* Disable the Cache Buses
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*
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* @param bus_id bus ID
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
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{
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(void) mask;
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uint32_t bus_mask = 0;
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if (bus_id == 0) {
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0);
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DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0);
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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/**
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* @brief Get Cache level and the ID of the vaddr
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*
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* @param vaddr_start virtual address start
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* @param len vaddr length
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* @param out_level cache level
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* @param out_id cache id
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*
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* @return true for valid
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
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{
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bool valid = false;
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uint32_t vaddr_end = vaddr_start + len - 1;
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valid |= ((vaddr_start >= SOC_DROM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DRAM1_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH));
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valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH));
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if (valid) {
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*out_level = 1;
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*out_id = 0;
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}
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return valid;
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,464 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for MMU register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/ext_mem_defs.h"
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#include "soc/dport_reg.h"
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#include "soc/dport_access.h"
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#include "hal/assert.h"
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#include "hal/mmu_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MMU_LL_PSRAM_ENTRY_START_ID 1152
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#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
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#define MMU_LL_END_DROM_ENTRY_ID (64 - 1)
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/**
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* Convert MMU virtual address to linear address
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*
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* @param vaddr virtual address
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*
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* @return linear address
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*/
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static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
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{
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return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
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}
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/**
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* Convert MMU linear address to virtual address
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*
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* @param laddr linear address
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* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
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* @param target virtual address aimed physical memory target, not used
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*
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* @return virtual address
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*/
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static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
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{
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(void)target;
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uint32_t vaddr_base = 0;
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if (vaddr_type == MMU_VADDR_DATA) {
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vaddr_base = SOC_MMU_DBUS_VADDR_BASE;
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} else {
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vaddr_base = SOC_MMU_IBUS_VADDR_BASE;
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}
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return vaddr_base | laddr;
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}
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/**
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* Get MMU page size
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*
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* @param mmu_id MMU ID
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*
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* @return MMU page size code
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*/
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__attribute__((always_inline))
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static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
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{
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//On esp32, MMU Page size is always 64KB
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(void)mmu_id;
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return MMU_PAGE_64KB;
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}
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/**
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* Set MMU page size
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*
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* @param size MMU page size
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*
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* @note On esp32, only supports `MMU_PAGE_64KB`
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*/
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__attribute__((always_inline))
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static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
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{
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//ONly supports `MMU_PAGE_64KB`
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}
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/**
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* Check if the external memory vaddr region is valid
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*
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* @param mmu_id MMU ID
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* @param vaddr_start start of the virtual address
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* @param len length, in bytes
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* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
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*
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* @return
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* True for valid
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*/
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__attribute__((always_inline))
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static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
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{
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(void)mmu_id;
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uint32_t vaddr_end = vaddr_start + len - 1;
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bool valid = false;
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if (type & MMU_VADDR_DATA) {
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valid |= (SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_end)) ||
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(SOC_ADDRESS_IN_DROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DROM0_CACHE(vaddr_end));
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}
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if (type & MMU_VADDR_INSTRUCTION) {
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valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) ||
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(SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_end)) ||
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(SOC_ADDRESS_IN_IROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IROM0_CACHE(vaddr_end));
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}
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return valid;
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}
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/**
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* Check if the paddr region is valid
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*
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* @param mmu_id MMU ID
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* @param paddr_start start of the physical address
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* @param len length, in bytes
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*
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* @return
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* True for valid
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*/
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static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
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{
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(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t offset = 0;
|
||||
uint32_t shift_code = 0;
|
||||
uint32_t vaddr_mask = 0;
|
||||
|
||||
//On ESP32, we only use PID0 and PID1
|
||||
if (SOC_ADDRESS_IN_DROM0_CACHE(vaddr)) {
|
||||
offset = 0;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)) {
|
||||
offset = 64;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_IRAM1_CACHE(vaddr)) {
|
||||
offset = 128;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_IROM0_CACHE(vaddr)) {
|
||||
offset = 192;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_DRAM1_CACHE(vaddr)) {
|
||||
//PSRAM page size 32KB
|
||||
offset = MMU_LL_PSRAM_ENTRY_START_ID;
|
||||
shift_code = 15;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK >> 1;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return offset + ((vaddr & vaddr_mask) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
if (target == MMU_TARGET_FLASH0) {
|
||||
shift_code = 16;
|
||||
} else {
|
||||
//PSRAM page size 32KB
|
||||
shift_code = 15;
|
||||
}
|
||||
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
switch (mmu_id) {
|
||||
case MMU_TABLE_CORE0:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], mmu_val);
|
||||
break;
|
||||
case MMU_TABLE_CORE1:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], mmu_val);
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t mmu_value;
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
switch (mmu_id) {
|
||||
case MMU_TABLE_CORE0:
|
||||
mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
|
||||
break;
|
||||
case MMU_TABLE_CORE1:
|
||||
mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id]);
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
return mmu_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
switch (mmu_id) {
|
||||
case MMU_TABLE_CORE0:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID);
|
||||
break;
|
||||
case MMU_TABLE_CORE1:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID);
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
|
||||
return (mmu_value & SOC_MMU_INVALID) ? false : true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id));
|
||||
|
||||
return (entry_id >= MMU_LL_PSRAM_ENTRY_START_ID) ? MMU_TARGET_PSRAM0 : MMU_TARGET_FLASH0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
|
||||
return (entry_id >= MMU_LL_PSRAM_ENTRY_START_ID) ? (mmu_value << 15) : (mmu_value << 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
if (target == MMU_TARGET_FLASH0) {
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
|
||||
if (!(mmu_value & SOC_MMU_INVALID)) {
|
||||
if (mmu_value == mmu_val) {
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
//For PSRAM, we only use PID 0/1. Its start entry ID is MMU_LL_PSRAM_ENTRY_START_ID (1152), and 128 entries are used for PSRAM
|
||||
for (int i = MMU_LL_PSRAM_ENTRY_START_ID; i < 1280; i++) {
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
|
||||
if (!(mmu_value & SOC_MMU_INVALID)) {
|
||||
if (mmu_value == mmu_val) {
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_base = 0;
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
if (entry_id < 64) {
|
||||
//first 64 entries are for DROM0
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x3f400000;
|
||||
} else if (entry_id >= 64 && entry_id < 128) {
|
||||
//second 64 entries are for IRAM0
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 64;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 128 && entry_id < 192) {
|
||||
//third 64 entries are for IRAM1
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 128;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 192 && entry_id < 256) {
|
||||
//fourth 64 entries are for IROM0
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 192;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= MMU_LL_PSRAM_ENTRY_START_ID) {
|
||||
//starting from 1152, 128 entries are for DRAM1
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= MMU_LL_PSRAM_ENTRY_START_ID;
|
||||
shift_code = 15;
|
||||
vaddr_base = 0x3f800000;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return vaddr_base + (entry_id << shift_code);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user