mirror of
https://github.com/espressif/esp-idf.git
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refactor(hal): extract cache && mmu HAL into esp_hal_cache
This commit is contained in:
morris
@@ -0,0 +1,38 @@
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idf_build_get_property(target IDF_TARGET)
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if(${target} STREQUAL "linux")
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return() # This component is not supported by the POSIX/Linux simulator
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endif()
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set(srcs)
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set(includes "include" "${target}/include")
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# The cache HAL is always built for normal apps, where the flash cache is enabled.
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# Pure RAM apps do not use the flash cache, except on chips where internal memory
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# accesses also go through the L1 cache (e.g. ESP32-P4): cache synchronization is
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# still required around internal RAM DMA operations on such chips.
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if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP OR CONFIG_SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE)
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if(${target} STREQUAL "esp32")
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list(APPEND srcs "esp32/cache_hal_esp32.c")
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else()
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list(APPEND srcs "cache_hal.c")
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endif()
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endif()
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# The MMU HAL implements external memory (flash/PSRAM) address translation.
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# Pure RAM apps do not map any external memory, so it is not built for them.
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if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP AND CONFIG_SOC_MMU_PERIPH_NUM)
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list(APPEND srcs "mmu_hal.c")
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endif()
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# Target-specific cache peripheral data
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if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/cache_periph.c")
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list(APPEND srcs "${target}/cache_periph.c")
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endif()
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idf_component_register(
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SRCS ${srcs}
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INCLUDE_DIRS ${includes}
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REQUIRES soc hal
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LDFRAGMENTS linker.lf
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)
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@@ -0,0 +1,39 @@
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# ESP Hardware Abstraction Layer for Cache and MMU
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_cache` component provides a **Hardware Abstraction Layer** for the cache and the external-memory MMU across all ESP-IDF supported targets. It serves as a foundation for higher-level drivers (DMA drivers, `esp_mm`, `spi_flash`, etc.) by offering a consistent interface to cache maintenance and external-memory address translation, while hiding the complexities of chip-specific implementations.
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## Architecture
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The HAL architecture consists of two primary layers:
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1. **HAL Layer (Upper)**: Defines the operational sequences and data structures required to interact with the cache and MMU, including:
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- Cache initialization, enabling and disabling
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- Cache maintenance operations (writeback, invalidate, writeback + invalidate, sync)
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- Cache freezing and preloading on supported chips
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- MMU mapping operations (virtual-to-physical address translation for flash and PSRAM)
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2. **Low-Level Layer (Bottom)**: Acts as a translation layer between the HAL and the register definitions in the `soc` component, handling:
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- Register access abstractions (`<target>/include/hal/cache_ll.h` and `<target>/include/hal/mmu_ll.h`)
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- Chip-specific register configurations
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- Hardware feature compatibility
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Implementation notes:
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- `cache_hal.c` implements the target-independent HAL sequences; ESP32 uses its dedicated ROM-compatible implementation (`esp32/cache_hal_esp32.c`).
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- `<target>/cache_periph.c` contains target-specific cache peripheral data.
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## Usage
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This component is primarily used by ESP-IDF drivers and system components such as `esp_driver_dma`, `esp_mm`, `esp_mspi`, `spi_flash` and `esp_psram`, as well as by the bootloader.
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For advanced developers implementing custom DMA or memory-management solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.
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## Dependencies
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- `soc`: Provides cache and MMU register definitions and SoC capabilities
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- `hal`: Core hardware abstraction utilities and macros
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@@ -0,0 +1,335 @@
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/*
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* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "hal/assert.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_types.h"
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#include "hal/cache_ll.h"
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#include "soc/soc_caps.h"
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/*------------------------------------------------------------------------------
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* Unified Cache Control
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* See cache_hal.h for more info about these HAL APIs
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* This file is in internal RAM.
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* Now this file doesn't compile on ESP32
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*----------------------------------------------------------------------------*/
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/**
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* Necessary hal contexts, could be maintained by upper layer in the future
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*/
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typedef struct {
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bool i_autoload_en;
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bool d_autoload_en;
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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// There's no register indicating if cache is enabled on these chips, use sw flag to save this state.
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bool i_cache_enabled;
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bool d_cache_enabled;
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#endif
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} cache_hal_state_t;
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typedef struct {
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cache_hal_state_t l1;
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cache_hal_state_t l2;
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} cache_hal_context_t;
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static cache_hal_context_t ctx;
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void s_cache_hal_init_ctx(void)
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{
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ctx.l1.d_autoload_en = cache_ll_is_cache_autoload_enabled(1, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
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ctx.l1.i_autoload_en = cache_ll_is_cache_autoload_enabled(1, CACHE_TYPE_INSTRUCTION, CACHE_LL_ID_ALL);
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ctx.l2.d_autoload_en = cache_ll_is_cache_autoload_enabled(2, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
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ctx.l2.i_autoload_en = cache_ll_is_cache_autoload_enabled(2, CACHE_TYPE_INSTRUCTION, CACHE_LL_ID_ALL);
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}
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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void cache_hal_init_l2_cache(const cache_hal_config_t *config)
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{
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cache_size_t cache_size;
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cache_line_size_t cache_line_size;
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if (config->l2_cache_size == 0x20000) {
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cache_size = CACHE_SIZE_128K;
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} else if (config->l2_cache_size == 0x40000) {
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cache_size = CACHE_SIZE_256K;
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} else {
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cache_size = CACHE_SIZE_512K;
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}
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if (config->l2_cache_line_size == 64) {
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cache_line_size = CACHE_LINE_SIZE_64B;
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} else {
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cache_line_size = CACHE_LINE_SIZE_128B;
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}
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Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size);
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Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
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}
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#endif
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void cache_hal_init(const cache_hal_config_t *config)
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{
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s_cache_hal_init_ctx();
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cache_ll_clk_init();
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if (CACHE_LL_LEVEL_EXT_MEM == 1) {
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cache_ll_enable_cache(1, CACHE_TYPE_ALL, CACHE_LL_ID_ALL, ctx.l1.i_autoload_en, ctx.l1.d_autoload_en);
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} else if (CACHE_LL_LEVEL_EXT_MEM == 2) {
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cache_ll_enable_cache(2, CACHE_TYPE_ALL, CACHE_LL_ID_ALL, ctx.l2.i_autoload_en, ctx.l2.d_autoload_en);
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}
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for (int i = 0; i < config->core_nums; i++) {
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cache_ll_l1_enable_bus(i, CACHE_LL_DEFAULT_DBUS_MASK);
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cache_ll_l1_enable_bus(i, CACHE_LL_DEFAULT_IBUS_MASK);
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}
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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ctx.l1.i_cache_enabled = 1;
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ctx.l1.d_cache_enabled = 1;
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ctx.l2.i_cache_enabled = 1;
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ctx.l2.d_cache_enabled = 1;
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#endif
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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cache_hal_init_l2_cache(config);
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#endif
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//CACHE_LL_PRELOAD_ARBITRARY will have better performance for preload
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cache_ll_preload_set_strategy(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL, CACHE_LL_PRELOAD_ARBITRARY);
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}
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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void s_update_cache_state(uint32_t cache_level, cache_type_t type, bool en)
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{
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HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
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switch (cache_level) {
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case 1:
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if (type == CACHE_TYPE_INSTRUCTION) {
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ctx.l1.i_cache_enabled = en;
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break;
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} else if (type == CACHE_TYPE_DATA) {
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ctx.l1.d_cache_enabled = en;
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break;
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} else if (type == CACHE_TYPE_ALL) {
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ctx.l1.i_cache_enabled = en;
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ctx.l1.d_cache_enabled = en;
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break;
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} else {
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HAL_ASSERT(false);
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break;
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}
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case 2:
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if (type == CACHE_TYPE_INSTRUCTION) {
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ctx.l2.i_cache_enabled = en;
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break;
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} else if (type == CACHE_TYPE_DATA) {
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ctx.l2.d_cache_enabled = en;
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break;
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} else if (type == CACHE_TYPE_ALL) {
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ctx.l2.i_cache_enabled = en;
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ctx.l2.d_cache_enabled = en;
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break;
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} else {
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HAL_ASSERT(false);
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break;
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}
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default:
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HAL_ASSERT(false);
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break;
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}
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}
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bool s_get_cache_state(uint32_t cache_level, cache_type_t type)
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{
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HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
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bool enabled = false;
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switch (cache_level) {
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case 1:
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if (type == CACHE_TYPE_INSTRUCTION) {
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enabled = ctx.l1.i_cache_enabled;
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break;
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} else if (type == CACHE_TYPE_DATA) {
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enabled = ctx.l1.d_cache_enabled;
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break;
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} else if (type == CACHE_TYPE_ALL) {
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enabled = ctx.l1.i_cache_enabled;
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enabled &= ctx.l1.d_cache_enabled;
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break;
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} else {
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HAL_ASSERT(false);
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break;
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}
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case 2:
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if (type == CACHE_TYPE_INSTRUCTION) {
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enabled = ctx.l2.i_cache_enabled;
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break;
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} else if (type == CACHE_TYPE_DATA) {
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enabled = ctx.l2.d_cache_enabled;
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break;
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} else if (type == CACHE_TYPE_ALL) {
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enabled = ctx.l2.i_cache_enabled;
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enabled &= ctx.l2.d_cache_enabled;
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break;
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} else {
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HAL_ASSERT(false);
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break;
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}
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default:
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HAL_ASSERT(false);
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break;
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}
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return enabled;
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}
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#endif //#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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void cache_hal_disable(uint32_t cache_level, cache_type_t type)
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{
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HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
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cache_ll_disable_cache(cache_level, type, CACHE_LL_ID_ALL);
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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s_update_cache_state(cache_level, type, false);
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#endif
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}
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void cache_hal_enable(uint32_t cache_level, cache_type_t type)
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{
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HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
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if (cache_level == 1) {
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cache_ll_enable_cache(1, type, CACHE_LL_ID_ALL, ctx.l1.i_autoload_en, ctx.l1.d_autoload_en);
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} else if (cache_level == 2) {
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cache_ll_enable_cache(2, type, CACHE_LL_ID_ALL, ctx.l2.i_autoload_en, ctx.l2.d_autoload_en);
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}
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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s_update_cache_state(cache_level, type, true);
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#endif
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}
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void cache_hal_suspend(uint32_t cache_level, cache_type_t type)
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{
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HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
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cache_ll_suspend_cache(cache_level, type, CACHE_LL_ID_ALL);
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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s_update_cache_state(cache_level, type, false);
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#endif
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}
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void cache_hal_resume(uint32_t cache_level, cache_type_t type)
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{
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HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
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if (cache_level == 1) {
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cache_ll_resume_cache(1, type, CACHE_LL_ID_ALL, ctx.l1.i_autoload_en, ctx.l1.d_autoload_en);
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} else if (cache_level == 2) {
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cache_ll_resume_cache(2, type, CACHE_LL_ID_ALL, ctx.l2.i_autoload_en, ctx.l2.d_autoload_en);
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}
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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s_update_cache_state(cache_level, type, true);
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#endif
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}
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bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type)
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{
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bool enabled = false;
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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enabled = s_get_cache_state(cache_level, type);
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#else
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enabled = cache_ll_is_cache_enabled(type);
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#endif //CACHE_LL_ENABLE_DISABLE_STATE_SW
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return enabled;
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}
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bool cache_hal_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
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{
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if (!out_level || !out_id) {
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return false;
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}
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return cache_ll_vaddr_to_cache_level_id(vaddr_start, len, out_level, out_id);
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}
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bool cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size)
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{
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bool valid = false;
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uint32_t cache_level = 0;
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uint32_t cache_id = 0;
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valid = cache_hal_vaddr_to_cache_level_id(vaddr, size, &cache_level, &cache_id);
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if (valid) {
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cache_ll_invalidate_addr(cache_level, CACHE_TYPE_ALL, cache_id, vaddr, size);
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}
|
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|
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return valid;
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}
|
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|
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#if SOC_CACHE_WRITEBACK_SUPPORTED
|
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bool cache_hal_writeback_addr(uint32_t vaddr, uint32_t size)
|
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{
|
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bool valid = false;
|
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uint32_t cache_level = 0;
|
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uint32_t cache_id = 0;
|
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|
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valid = cache_hal_vaddr_to_cache_level_id(vaddr, size, &cache_level, &cache_id);
|
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if (valid) {
|
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cache_ll_writeback_addr(cache_level, CACHE_TYPE_DATA, cache_id, vaddr, size);
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
#endif //#if SOC_CACHE_WRITEBACK_SUPPORTED
|
||||
|
||||
#if SOC_CACHE_FREEZE_SUPPORTED
|
||||
void cache_hal_freeze(uint32_t cache_level, cache_type_t type)
|
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{
|
||||
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
|
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|
||||
cache_ll_freeze_cache(cache_level, type, CACHE_LL_ID_ALL);
|
||||
}
|
||||
|
||||
void cache_hal_unfreeze(uint32_t cache_level, cache_type_t type)
|
||||
{
|
||||
HAL_ASSERT(cache_level && (cache_level <= CACHE_LL_LEVEL_NUMS));
|
||||
|
||||
cache_ll_unfreeze_cache(cache_level, type, CACHE_LL_ID_ALL);
|
||||
}
|
||||
#endif //#if SOC_CACHE_FREEZE_SUPPORTED
|
||||
|
||||
uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
|
||||
{
|
||||
HAL_ASSERT(cache_level <= CACHE_LL_LEVEL_NUMS);
|
||||
uint32_t line_size = 0;
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
line_size = cache_ll_get_line_size(cache_level, type, CACHE_LL_ID_ALL);
|
||||
#else
|
||||
if (cache_level == CACHE_LL_LEVEL_EXT_MEM) {
|
||||
line_size = cache_ll_get_line_size(cache_level, type, CACHE_LL_ID_ALL);
|
||||
}
|
||||
#endif
|
||||
|
||||
return line_size;
|
||||
}
|
||||
|
||||
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
cache_ll_preload(cache_level, type, CACHE_LL_ID_ALL, vaddr, size, order);
|
||||
}
|
||||
|
||||
void cache_hal_preload_wait_done(uint32_t cache_level, cache_type_t type)
|
||||
{
|
||||
cache_ll_preload_wait_done(cache_level, type, CACHE_LL_ID_ALL);
|
||||
}
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "hal/cache_ll.h"
|
||||
#include "hal/cache_hal.h"
|
||||
|
||||
static uint32_t s_cache_status[2];
|
||||
|
||||
void cache_hal_init(const cache_hal_config_t *config)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* On ESP32, The cache_hal_suspend()/cache_hal_resume() are replacements
|
||||
* for Cache_Read_Disable()/Cache_Read_Enable() in ROM.
|
||||
* There's a bug that Cache_Read_Disable requires a call to Cache_Flush
|
||||
* before Cache_Read_Enable, even if cached data was not modified.
|
||||
*/
|
||||
void cache_hal_suspend(uint32_t cache_level, cache_type_t type)
|
||||
{
|
||||
s_cache_status[0] = cache_ll_l1_get_enabled_bus(0);
|
||||
cache_ll_l1_disable_cache(0);
|
||||
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
s_cache_status[1] = cache_ll_l1_get_enabled_bus(1);
|
||||
cache_ll_l1_disable_cache(1);
|
||||
#endif
|
||||
}
|
||||
|
||||
void cache_hal_resume(uint32_t cache_level, cache_type_t type)
|
||||
{
|
||||
cache_ll_l1_enable_cache(0);
|
||||
cache_ll_l1_enable_bus(0, s_cache_status[0]);
|
||||
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
cache_ll_l1_enable_cache(1);
|
||||
cache_ll_l1_enable_bus(1, s_cache_status[1]);
|
||||
#endif
|
||||
}
|
||||
|
||||
bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type)
|
||||
{
|
||||
bool result = cache_ll_l1_is_cache_enabled(0, CACHE_TYPE_ALL);
|
||||
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
result = result && cache_ll_l1_is_cache_enabled(1, CACHE_TYPE_ALL);
|
||||
#endif
|
||||
return result;
|
||||
}
|
||||
|
||||
bool cache_hal_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
if (!out_level || !out_id) {
|
||||
return false;
|
||||
}
|
||||
return cache_ll_vaddr_to_cache_level_id(vaddr_start, len, out_level, out_id);
|
||||
}
|
||||
|
||||
uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type)
|
||||
{
|
||||
HAL_ASSERT(cache_level <= CACHE_LL_LEVEL_NUMS);
|
||||
|
||||
uint32_t line_size = 0;
|
||||
|
||||
if (cache_level == CACHE_LL_LEVEL_EXT_MEM) {
|
||||
line_size = 4;
|
||||
}
|
||||
|
||||
return line_size;
|
||||
}
|
||||
|
||||
bool cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
//esp32 doesn't support invalidate certain addr
|
||||
abort();
|
||||
}
|
||||
|
||||
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
//not supported, for compatibility
|
||||
}
|
||||
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CACHE_LL_ID_ALL 2 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
|
||||
/**
|
||||
* @brief enable a cache unit
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_enable_cache(uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
|
||||
if (cache_id == 0) {
|
||||
DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
|
||||
} else {
|
||||
DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief disable a cache unit
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_cache(uint32_t cache_id)
|
||||
{
|
||||
if (cache_id == 0) {
|
||||
while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
|
||||
;
|
||||
}
|
||||
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
|
||||
} else {
|
||||
while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
|
||||
;
|
||||
}
|
||||
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the status of cache if it is enabled or not
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param type see `cache_type_t`
|
||||
* @return enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_cache_enabled(uint32_t cache_id, cache_type_t type)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
(void) type; //On 32 it shares between I and D cache
|
||||
|
||||
bool enabled;
|
||||
if (cache_id == 0) {
|
||||
enabled = DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
|
||||
} else {
|
||||
enabled = DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_HIGH) {
|
||||
HAL_ASSERT(false); //out of range
|
||||
} else if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
|
||||
} else if (vaddr_start >= SOC_IRAM1_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));
|
||||
} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0));
|
||||
} else if (vaddr_start >= SOC_DRAM1_CACHE_ADDRESS_LOW) {
|
||||
HAL_ASSERT(vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
|
||||
} else if (vaddr_start >= SOC_DROM0_CACHE_ADDRESS_LOW) {
|
||||
HAL_ASSERT(vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
* @param enable 1: enable; 0: disable
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
(void) mask;
|
||||
uint32_t bus_mask = 0;
|
||||
if (bus_id == 0) {
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
|
||||
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0);
|
||||
|
||||
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
|
||||
} else {
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0);
|
||||
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0);
|
||||
|
||||
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns enabled buses for a given core
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*
|
||||
* @return State of enabled buses
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
if (cache_id == 0) {
|
||||
uint32_t bus_mask = DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG);
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));
|
||||
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));
|
||||
} else {
|
||||
uint32_t bus_mask = DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG);
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0));
|
||||
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0));
|
||||
}
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
* @param enable 1: enable; 0: disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
(void) mask;
|
||||
uint32_t bus_mask = 0;
|
||||
if (bus_id == 0) {
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
|
||||
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0);
|
||||
|
||||
DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
|
||||
} else {
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0);
|
||||
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0);
|
||||
bus_mask = bus_mask | ((mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0);
|
||||
|
||||
DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= ((vaddr_start >= SOC_DROM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DRAM1_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH));
|
||||
valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,464 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/dport_access.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_PSRAM_ENTRY_START_ID 1152
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (64 - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (vaddr_type == MMU_VADDR_DATA) {
|
||||
vaddr_base = SOC_MMU_DBUS_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_IBUS_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
//On esp32, MMU Page size is always 64KB
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*
|
||||
* @note On esp32, only supports `MMU_PAGE_64KB`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
//ONly supports `MMU_PAGE_64KB`
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
bool valid = false;
|
||||
|
||||
if (type & MMU_VADDR_DATA) {
|
||||
valid |= (SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_end)) ||
|
||||
(SOC_ADDRESS_IN_DROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DROM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
if (type & MMU_VADDR_INSTRUCTION) {
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) ||
|
||||
(SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_end)) ||
|
||||
(SOC_ADDRESS_IN_IROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IROM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t offset = 0;
|
||||
uint32_t shift_code = 0;
|
||||
uint32_t vaddr_mask = 0;
|
||||
|
||||
//On ESP32, we only use PID0 and PID1
|
||||
if (SOC_ADDRESS_IN_DROM0_CACHE(vaddr)) {
|
||||
offset = 0;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)) {
|
||||
offset = 64;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_IRAM1_CACHE(vaddr)) {
|
||||
offset = 128;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_IROM0_CACHE(vaddr)) {
|
||||
offset = 192;
|
||||
shift_code = 16;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK;
|
||||
} else if (SOC_ADDRESS_IN_DRAM1_CACHE(vaddr)) {
|
||||
//PSRAM page size 32KB
|
||||
offset = MMU_LL_PSRAM_ENTRY_START_ID;
|
||||
shift_code = 15;
|
||||
vaddr_mask = SOC_MMU_VADDR_MASK >> 1;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return offset + ((vaddr & vaddr_mask) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
if (target == MMU_TARGET_FLASH0) {
|
||||
shift_code = 16;
|
||||
} else {
|
||||
//PSRAM page size 32KB
|
||||
shift_code = 15;
|
||||
}
|
||||
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
switch (mmu_id) {
|
||||
case MMU_TABLE_CORE0:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], mmu_val);
|
||||
break;
|
||||
case MMU_TABLE_CORE1:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], mmu_val);
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t mmu_value;
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
switch (mmu_id) {
|
||||
case MMU_TABLE_CORE0:
|
||||
mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
|
||||
break;
|
||||
case MMU_TABLE_CORE1:
|
||||
mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id]);
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
return mmu_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
switch (mmu_id) {
|
||||
case MMU_TABLE_CORE0:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID);
|
||||
break;
|
||||
case MMU_TABLE_CORE1:
|
||||
DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID);
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
|
||||
return (mmu_value & SOC_MMU_INVALID) ? false : true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id));
|
||||
|
||||
return (entry_id >= MMU_LL_PSRAM_ENTRY_START_ID) ? MMU_TARGET_PSRAM0 : MMU_TARGET_FLASH0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
|
||||
return (entry_id >= MMU_LL_PSRAM_ENTRY_START_ID) ? (mmu_value << 15) : (mmu_value << 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
|
||||
DPORT_INTERRUPT_DISABLE();
|
||||
if (target == MMU_TARGET_FLASH0) {
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
|
||||
if (!(mmu_value & SOC_MMU_INVALID)) {
|
||||
if (mmu_value == mmu_val) {
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
//For PSRAM, we only use PID 0/1. Its start entry ID is MMU_LL_PSRAM_ENTRY_START_ID (1152), and 128 entries are used for PSRAM
|
||||
for (int i = MMU_LL_PSRAM_ENTRY_START_ID; i < 1280; i++) {
|
||||
uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
|
||||
if (!(mmu_value & SOC_MMU_INVALID)) {
|
||||
if (mmu_value == mmu_val) {
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
DPORT_INTERRUPT_RESTORE();
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_base = 0;
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
if (entry_id < 64) {
|
||||
//first 64 entries are for DROM0
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x3f400000;
|
||||
} else if (entry_id >= 64 && entry_id < 128) {
|
||||
//second 64 entries are for IRAM0
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 64;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 128 && entry_id < 192) {
|
||||
//third 64 entries are for IRAM1
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 128;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 192 && entry_id < 256) {
|
||||
//fourth 64 entries are for IROM0
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 192;
|
||||
shift_code = 16;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= MMU_LL_PSRAM_ENTRY_START_ID) {
|
||||
//starting from 1152, 128 entries are for DRAM1
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= MMU_LL_PSRAM_ENTRY_START_ID;
|
||||
shift_code = 15;
|
||||
vaddr_base = 0x3f800000;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return vaddr_base + (entry_id << shift_code);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,437 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32c2/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0)
|
||||
|
||||
#define CACHE_LL_L1_ILG_EVENT_MASK (0x23)
|
||||
#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5)
|
||||
#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1)
|
||||
#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0)
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
//On ESP32C2, the auto preload flag is always 0
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD 0
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
bool enabled = false;
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void) type;
|
||||
Cache_Disable_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_ICache(CACHE_LL_L1_ICACHE_AUTOLOAD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Suspend_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_ICache(CACHE_LL_L1_ICACHE_AUTOLOAD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache is enabled or not. On ESP32C2, instructions and data share Cache
|
||||
*
|
||||
* @param type see `cache_type_t`
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
|
||||
{
|
||||
bool enabled = false;
|
||||
enabled = REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE);
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Invalidate_ICache_All();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (no-op)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
(void)strategy;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (no-op; ROM has no manual preload API)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
(void)vaddr;
|
||||
(void)size;
|
||||
(void)order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (no-op)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
|
||||
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
|
||||
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
|
||||
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
|
||||
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
|
||||
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C2. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C2. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C2. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache illegal error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C2. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache illegal error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C2. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache illegal error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C2. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,388 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (vaddr_type == MMU_VADDR_DATA) {
|
||||
vaddr_base = SOC_MMU_DBUS_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_IBUS_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t page_size_code = REG_GET_FIELD(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_MMU_PAGE_SIZE);
|
||||
return (page_size_code == 0) ? MMU_PAGE_16KB : (page_size_code == 1) ? MMU_PAGE_32KB : MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
uint8_t reg_val = (size == MMU_PAGE_16KB) ? 0 : (size == MMU_PAGE_32KB) ? 1 : 2;
|
||||
REG_SET_FIELD(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_MMU_PAGE_SIZE, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
bool valid = false;
|
||||
|
||||
if (type & MMU_VADDR_INSTRUCTION) {
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
if (type & MMU_VADDR_DATA) {
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(target == MMU_TARGET_FLASH0);
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | SOC_MMU_ACCESS_FLASH | SOC_MMU_VALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return MMU_TARGET_FLASH0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,455 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32c3/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0)
|
||||
|
||||
#define CACHE_LL_L1_ILG_EVENT_MASK (0x23)
|
||||
#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5)
|
||||
#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1)
|
||||
#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0)
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<2)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(EXTMEM_ICACHE_AUTOLOAD_CTRL_REG, EXTMEM_ICACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void) type;
|
||||
Cache_Disable_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Suspend_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache is enabled or not. On ESP32C3, instructions and data share Cache
|
||||
*
|
||||
* @param type see `cache_type_t`
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
|
||||
{
|
||||
bool enabled = false;
|
||||
enabled = REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE);
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Invalidate_ICache_All();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (no-op)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
(void)strategy;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (L1 ICache only)
|
||||
*
|
||||
* Starts preload for the given region and does not wait. Use
|
||||
* cache_ll_preload_wait_done() to wait for completion.
|
||||
* DATA type is no-op.
|
||||
*
|
||||
* @param cache_level level of the cache (must be CACHE_LL_LEVEL_EXT_MEM)
|
||||
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
|
||||
* @param cache_id id of the cache (unused on C3; pass 0 or CACHE_LL_ID_ALL)
|
||||
* @param vaddr start virtual address of the preload region
|
||||
* @param size size of the preload region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
Cache_Start_ICache_Preload(vaddr, size, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
while (Cache_ICache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
|
||||
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
|
||||
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
|
||||
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
|
||||
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0);
|
||||
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache illegal error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache illegal error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache illegal error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,324 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_types.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - 0x10000)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (vaddr_type == MMU_VADDR_DATA) {
|
||||
vaddr_base = SOC_MMU_DBUS_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_IBUS_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
//On esp32c3, MMU Page size is always 64KB
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*
|
||||
* @note On esp32c3, only supports `MMU_PAGE_64KB`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
HAL_ASSERT(size == MMU_PAGE_64KB);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
bool valid = false;
|
||||
|
||||
if (type & MMU_VADDR_INSTRUCTION) {
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
if (type & MMU_VADDR_DATA) {
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
return paddr >> 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(target == MMU_TARGET_FLASH0);
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | SOC_MMU_ACCESS_FLASH | SOC_MMU_VALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return MMU_TARGET_FLASH0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t laddr = entry_id << 16;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-C5 cache profile counter units.
|
||||
*
|
||||
* Single cache level shared by instructions and data (the flash/PSRAM
|
||||
* cache, 32-byte lines), with two request buses: bus0 carries instruction
|
||||
* fetches, bus1 carries data accesses. Counter semantics match the
|
||||
* ESP32-P4. The hit/miss/conflict counters use the BUS0/BUS1 register
|
||||
* names while the corresponding next-level counters use the DBUS0/DBUS1
|
||||
* names. Only the CPU request buses are exposed here.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,472 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/cache_reg.h"
|
||||
#include "soc/cache_struct.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "rom/cache.h"
|
||||
#include "hal/cache_periph.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32c5/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void) type;
|
||||
Cache_Disable_Cache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Suspend_Cache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Invalidate_All();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writeback cache supported addr
|
||||
*
|
||||
* Writeback a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be written back
|
||||
* @param size size of the region to be written back
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_WriteBack_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (L1 unified)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_id;
|
||||
(void)type;
|
||||
if (cache_level == CACHE_LL_LEVEL_EXT_MEM || cache_level == CACHE_LL_LEVEL_ALL) {
|
||||
CACHE.l1_icache_ctrl.l1_icache_undef_op = strategy;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (L1 unified)
|
||||
*
|
||||
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
|
||||
*
|
||||
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache (unused; pass 0)
|
||||
* @param vaddr start virtual address of the preload region
|
||||
* @param size size of the preload region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
(void)type;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
Cache_Start_Preload(vaddr, size, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
(void)type;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
while (Cache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_Line_Size(CACHE_MAP_FLASH_CACHE);
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
//c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
|
||||
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache fail tracer
|
||||
*
|
||||
* @param cache_id cache ID
|
||||
* @param en enable / disable
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
|
||||
{
|
||||
CACHE.trace_ena.l1_cache_trace_ena = en;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
CACHE.l1_cache_acs_fail_int_ena.val |= mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
CACHE.l1_cache_acs_fail_int_clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return CACHE.l1_cache_acs_fail_int_st.val & mask;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Cache Profile Counter Related
|
||||
-----------------------------------------------------------------------------*/
|
||||
#define CACHE_LL_PROFILE_CNT_ENA_MASK (CACHE_L1_BUS0_CNT_ENA | CACHE_L1_BUS1_CNT_ENA)
|
||||
#define CACHE_LL_PROFILE_CNT_CLR_MASK (CACHE_L1_BUS0_CNT_CLR | CACHE_L1_BUS1_CNT_CLR)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the cache profile counters
|
||||
*
|
||||
* @param ena True to enable, false to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_profile_counter(bool ena)
|
||||
{
|
||||
if (ena) {
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
} else {
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset all cache profile counters to zero
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clear_profile_counter(void)
|
||||
{
|
||||
/* clear bits are write-to-trigger and self-clearing */
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_CLR_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one counter of a cache profile counter unit
|
||||
*
|
||||
* @param unit Unit index, 0 to SOC_CACHE_CNT_UNITS_NUM - 1
|
||||
* @param counter Counter to read
|
||||
* @param[out] value Counter value, only written if the counter exists
|
||||
*
|
||||
* @return True if the unit has this counter, false otherwise
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_get_profile_counter(int unit, cache_profile_counter_t counter, uint32_t *value)
|
||||
{
|
||||
HAL_ASSERT(unit < SOC_CACHE_CNT_UNITS_NUM);
|
||||
uint32_t reg = cache_periph_profile_counter_units[unit].counter_reg[counter];
|
||||
if (reg == 0) {
|
||||
return false;
|
||||
}
|
||||
*value = REG_READ(reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,437 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "esp_fault.h"
|
||||
#if SOC_EFUSE_SUPPORTED
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_FLASH_MMU_ID 0
|
||||
#define MMU_LL_PSRAM_MMU_ID 0
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
(void)vaddr_type;
|
||||
//On ESP32C5, I/D share the same vaddr range
|
||||
return SOC_MMU_IBUS_VADDR_BASE | laddr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
#if SOC_EFUSE_SUPPORTED
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
HAL_ASSERT(size == MMU_PAGE_64KB);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
// For PSRAM case, avoid encryption due to a bug in the hardware
|
||||
if (!(target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() <= 100)) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
}
|
||||
mmu_val |= (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
|
||||
mmu_raw_value = mmu_val | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
|
||||
#if !BOOTLOADER_BUILD && !ESP_TEE_BUILD
|
||||
// Anti-FI check to confirm the encryption status for PSRAM entry.
|
||||
// This avoids a potential FI attacks to keep PSRAM unencrypted and
|
||||
// hence read out plaintext in execute from PSRAM model.
|
||||
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
|
||||
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
|
||||
} else {
|
||||
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100));
|
||||
}
|
||||
#endif // !BOOTLOADER_BUILD && !ESP_TEE_BUILD
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a PSRAM MMU entry without the SENSITIVE bit, used only for the
|
||||
* carved-out unencrypted region (see CONFIG_SPIRAM_ENC_EXEMPT).
|
||||
*
|
||||
* No anti-FI check: the SENSITIVE bit is intentionally clear, and an FI flip
|
||||
* that sets it would force decryption of plaintext data (garbage, fails safe).
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry_no_enc(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value = mmu_val | SOC_MMU_ACCESS_SPIRAM | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
|
||||
}
|
||||
if (!(mmu_raw_value & SOC_MMU_VALID)) {
|
||||
return 0;
|
||||
}
|
||||
ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_target_t target = ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_ACCESS_SPIRAM) == 0) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0;
|
||||
return target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
|
||||
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-C6 cache profile counter units.
|
||||
*
|
||||
* Single cache level shared by instructions and data (the flash cache,
|
||||
* 32-byte lines), with one instruction bus and one data bus. Counter
|
||||
* semantics match the ESP32-P4. There is one next-level counter per bus
|
||||
* (no read/write split), mapped here to line_fills. The cache is
|
||||
* read-only (no PSRAM, no write-back — see SOC_CACHE_WRITEBACK_SUPPORTED),
|
||||
* so there are no write-back counters.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = EXTMEM_L1_IBUS_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = EXTMEM_L1_IBUS_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = EXTMEM_L1_DBUS_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = EXTMEM_L1_DBUS_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,449 @@
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_periph.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32c6/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4)
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG, EXTMEM_L1_CACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void) type;
|
||||
Cache_Disable_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Suspend_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Invalidate_ICache_All();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_id;
|
||||
(void)type;
|
||||
if (cache_level == CACHE_LL_LEVEL_EXT_MEM || cache_level == CACHE_LL_LEVEL_ALL) {
|
||||
REG_SET_FIELD(EXTMEM_L1_CACHE_CTRL_REG, EXTMEM_L1_CACHE_UNDEF_OP, strategy);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (L1 ICache only)
|
||||
*
|
||||
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
|
||||
* DATA type is no-op.
|
||||
*
|
||||
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
|
||||
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
|
||||
* @param cache_id id of the cache (unused; pass 0)
|
||||
* @param vaddr start virtual address of the preload region
|
||||
* @param size size of the preload region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
Cache_Start_ICache_Preload(vaddr, size, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
while (Cache_ICache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
//c6 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
|
||||
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
|
||||
REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
|
||||
REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
|
||||
REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
|
||||
REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Cache Profile Counter Related
|
||||
-----------------------------------------------------------------------------*/
|
||||
#define CACHE_LL_PROFILE_CNT_ENA_MASK (EXTMEM_L1_IBUS_CNT_ENA | EXTMEM_L1_DBUS_CNT_ENA)
|
||||
#define CACHE_LL_PROFILE_CNT_CLR_MASK (EXTMEM_L1_IBUS_CNT_CLR | EXTMEM_L1_DBUS_CNT_CLR)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the cache profile counters
|
||||
*
|
||||
* @param ena True to enable, false to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_profile_counter(bool ena)
|
||||
{
|
||||
if (ena) {
|
||||
REG_SET_BIT(EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
} else {
|
||||
REG_CLR_BIT(EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset all cache profile counters to zero
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clear_profile_counter(void)
|
||||
{
|
||||
/* clear bits are write-to-trigger and self-clearing */
|
||||
REG_SET_BIT(EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_CLR_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one counter of a cache profile counter unit
|
||||
*
|
||||
* @param unit Unit index, 0 to SOC_CACHE_CNT_UNITS_NUM - 1
|
||||
* @param counter Counter to read
|
||||
* @param[out] value Counter value, only written if the counter exists
|
||||
*
|
||||
* @return True if the unit has this counter, false otherwise
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_get_profile_counter(int unit, cache_profile_counter_t counter, uint32_t *value)
|
||||
{
|
||||
HAL_ASSERT(unit < SOC_CACHE_CNT_UNITS_NUM);
|
||||
uint32_t reg = cache_periph_profile_counter_units[unit].counter_reg[counter];
|
||||
if (reg == 0) {
|
||||
return false;
|
||||
}
|
||||
*value = REG_READ(reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,409 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
(void)vaddr_type;
|
||||
//On ESP32C6, I/D share the same vaddr range
|
||||
return SOC_MMU_IBUS_VADDR_BASE | laddr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
|
||||
return (page_size_code == 0) ? MMU_PAGE_64KB : \
|
||||
(page_size_code == 1) ? MMU_PAGE_32KB : \
|
||||
(page_size_code == 2) ? MMU_PAGE_16KB : \
|
||||
MMU_PAGE_8KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \
|
||||
(size == MMU_PAGE_32KB) ? 1 : \
|
||||
(size == MMU_PAGE_16KB) ? 2 : \
|
||||
(size == MMU_PAGE_8KB) ? 3 : 0;
|
||||
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
|
||||
mmu_raw_value = mmu_val | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
|
||||
}
|
||||
if (!(mmu_raw_value & SOC_MMU_VALID)) {
|
||||
return 0;
|
||||
}
|
||||
ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return MMU_TARGET_FLASH0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
|
||||
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-C61 cache profile counter units.
|
||||
*
|
||||
* Single cache level shared by instructions and data (the flash/PSRAM
|
||||
* cache), with two request buses: bus0 carries instruction fetches, bus1
|
||||
* carries data accesses (same bus arrangement as the ESP32-C5). bus0's
|
||||
* next-level counters use the BUS0 register names while bus1's use the
|
||||
* DBUS1 names.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,471 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/cache_reg.h"
|
||||
#include "soc/cache_struct.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_periph.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32c61/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void) type;
|
||||
Cache_Disable_Cache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Suspend_Cache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Invalidate_All();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writeback cache supported addr
|
||||
*
|
||||
* Writeback a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be written back
|
||||
* @param size size of the region to be written back
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_WriteBack_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (L1 unified)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_id;
|
||||
(void)type;
|
||||
if (cache_level == CACHE_LL_LEVEL_EXT_MEM || cache_level == CACHE_LL_LEVEL_ALL) {
|
||||
CACHE.l1_cache_ctrl.l1_icache_undef_op = strategy;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (L1 unified)
|
||||
*
|
||||
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
|
||||
*
|
||||
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache (unused; pass 0)
|
||||
* @param vaddr start virtual address of the preload region
|
||||
* @param size size of the preload region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
(void)type;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
Cache_Start_Preload(vaddr, size, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
(void)type;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
while (Cache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
//c61 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
|
||||
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache fail tracer
|
||||
*
|
||||
* @param cache_id cache ID
|
||||
* @param en enable / disable
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
|
||||
{
|
||||
CACHE.trace_ena.l1_cache_trace_ena = en;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
CACHE.l1_cache_acs_fail_int_ena.val |= mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
CACHE.l1_cache_acs_fail_int_clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return CACHE.l1_cache_acs_fail_int_st.val & mask;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Cache Profile Counter Related
|
||||
-----------------------------------------------------------------------------*/
|
||||
#define CACHE_LL_PROFILE_CNT_ENA_MASK (CACHE_L1_BUS0_CNT_ENA | CACHE_L1_BUS1_CNT_ENA)
|
||||
#define CACHE_LL_PROFILE_CNT_CLR_MASK (CACHE_L1_BUS0_CNT_CLR | CACHE_L1_BUS1_CNT_CLR)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the cache profile counters
|
||||
*
|
||||
* @param ena True to enable, false to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_profile_counter(bool ena)
|
||||
{
|
||||
if (ena) {
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
} else {
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset all cache profile counters to zero
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clear_profile_counter(void)
|
||||
{
|
||||
/* clear bits are write-to-trigger and self-clearing */
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_CLR_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one counter of a cache profile counter unit
|
||||
*
|
||||
* @param unit Unit index, 0 to SOC_CACHE_CNT_UNITS_NUM - 1
|
||||
* @param counter Counter to read
|
||||
* @param[out] value Counter value, only written if the counter exists
|
||||
*
|
||||
* @return True if the unit has this counter, false otherwise
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_get_profile_counter(int unit, cache_profile_counter_t counter, uint32_t *value)
|
||||
{
|
||||
HAL_ASSERT(unit < SOC_CACHE_CNT_UNITS_NUM);
|
||||
uint32_t reg = cache_periph_profile_counter_units[unit].counter_reg[counter];
|
||||
if (reg == 0) {
|
||||
return false;
|
||||
}
|
||||
*value = REG_READ(reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,443 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_fault.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_FLASH_MMU_ID 0
|
||||
#define MMU_LL_PSRAM_MMU_ID 0
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
(void)vaddr_type;
|
||||
//On ESP32C61, I/D share the same vaddr range
|
||||
return SOC_MMU_IBUS_VADDR_BASE | laddr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE);
|
||||
return (page_size_code == 0) ? MMU_PAGE_64KB : \
|
||||
(page_size_code == 1) ? MMU_PAGE_32KB : \
|
||||
(page_size_code == 2) ? MMU_PAGE_16KB : \
|
||||
MMU_PAGE_8KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \
|
||||
(size == MMU_PAGE_32KB) ? 1 : \
|
||||
(size == MMU_PAGE_16KB) ? 2 : \
|
||||
(size == MMU_PAGE_8KB) ? 3 : 0;
|
||||
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
// For PSRAM case, avoid encryption due to a bug in the hardware
|
||||
if (!(target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() <= 100)) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
}
|
||||
mmu_val |= (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
|
||||
mmu_raw_value = mmu_val | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
#if !BOOTLOADER_BUILD && !ESP_TEE_BUILD
|
||||
// Anti-FI check to confirm the encryption status for PSRAM entry.
|
||||
// This avoids a potential FI attacks to keep PSRAM unencrypted and
|
||||
// hence read out plaintext in execute from PSRAM model.
|
||||
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
|
||||
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
|
||||
} else {
|
||||
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100));
|
||||
}
|
||||
#endif // !BOOTLOADER_BUILD && !ESP_TEE_BUILD
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a PSRAM MMU entry without the SENSITIVE bit, used only for the
|
||||
* carved-out unencrypted region (see CONFIG_SPIRAM_ENC_EXEMPT).
|
||||
*
|
||||
* No anti-FI check: the SENSITIVE bit is intentionally clear, and an FI flip
|
||||
* that sets it would force decryption of plaintext data (garbage, fails safe).
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry_no_enc(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value = mmu_val | SOC_MMU_ACCESS_SPIRAM | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
|
||||
}
|
||||
if (!(mmu_raw_value & SOC_MMU_VALID)) {
|
||||
return 0;
|
||||
}
|
||||
ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_target_t target = ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_ACCESS_SPIRAM) == 0) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0;
|
||||
return target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
|
||||
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-H2 cache profile counter units.
|
||||
*
|
||||
* Single cache level shared by instructions and data (the flash cache,
|
||||
* 32-byte lines), with two request buses: bus0 carries instruction
|
||||
* fetches, bus1 carries data accesses. There is one next-level counter
|
||||
* per bus (no read/write split), mapped here to line_fills. The cache is
|
||||
* read-only (no PSRAM, no write-back — see SOC_CACHE_WRITEBACK_SUPPORTED),
|
||||
* so there are no write-back counters.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,447 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_periph.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32h2/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4)
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void) type;
|
||||
Cache_Disable_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Suspend_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Invalidate_ICache_All();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (no-op)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
(void)strategy;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (L1 ICache only)
|
||||
*
|
||||
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
|
||||
* DATA type is no-op.
|
||||
*
|
||||
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
|
||||
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
|
||||
* @param cache_id id of the cache (unused; pass 0)
|
||||
* @param vaddr start virtual address of the preload region
|
||||
* @param size size of the preload region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
Cache_Start_ICache_Preload(vaddr, size, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
while (Cache_ICache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
//h2 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
|
||||
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID, not used on C3. For compabitlity
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Cache Profile Counter Related
|
||||
-----------------------------------------------------------------------------*/
|
||||
#define CACHE_LL_PROFILE_CNT_ENA_MASK (CACHE_L1_BUS0_CNT_ENA | CACHE_L1_BUS1_CNT_ENA)
|
||||
#define CACHE_LL_PROFILE_CNT_CLR_MASK (CACHE_L1_BUS0_CNT_CLR | CACHE_L1_BUS1_CNT_CLR)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the cache profile counters
|
||||
*
|
||||
* @param ena True to enable, false to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_profile_counter(bool ena)
|
||||
{
|
||||
if (ena) {
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
} else {
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset all cache profile counters to zero
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clear_profile_counter(void)
|
||||
{
|
||||
/* clear bits are write-to-trigger and self-clearing */
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_CLR_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one counter of a cache profile counter unit
|
||||
*
|
||||
* @param unit Unit index, 0 to SOC_CACHE_CNT_UNITS_NUM - 1
|
||||
* @param counter Counter to read
|
||||
* @param[out] value Counter value, only written if the counter exists
|
||||
*
|
||||
* @return True if the unit has this counter, false otherwise
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_get_profile_counter(int unit, cache_profile_counter_t counter, uint32_t *value)
|
||||
{
|
||||
HAL_ASSERT(unit < SOC_CACHE_CNT_UNITS_NUM);
|
||||
uint32_t reg = cache_periph_profile_counter_units[unit].counter_reg[counter];
|
||||
if (reg == 0) {
|
||||
return false;
|
||||
}
|
||||
*value = REG_READ(reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,414 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
(void)vaddr_type;
|
||||
//On ESP32C6, I/D share the same vaddr range
|
||||
return SOC_MMU_IBUS_VADDR_BASE | laddr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
|
||||
return (page_size_code == 0) ? MMU_PAGE_64KB : \
|
||||
(page_size_code == 1) ? MMU_PAGE_32KB : \
|
||||
(page_size_code == 2) ? MMU_PAGE_16KB : \
|
||||
MMU_PAGE_8KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \
|
||||
(size == MMU_PAGE_32KB) ? 1 : \
|
||||
(size == MMU_PAGE_16KB) ? 2 : \
|
||||
(size == MMU_PAGE_8KB) ? 3 : 0;
|
||||
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, uint32_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
/* Note: for ESP32-H2, invert invalid bit for compatible with upper-layer software */
|
||||
mmu_raw_value = mmu_val ^ SOC_MMU_INVALID_MASK;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
|
||||
}
|
||||
/* Note: for ESP32-H2, invert invalid bit for compatible with upper-layer software */
|
||||
ret = mmu_raw_value ^ SOC_MMU_INVALID_MASK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return MMU_TARGET_FLASH0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
|
||||
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-H21 cache profile counter units.
|
||||
*
|
||||
* Single cache level shared by instructions and data (the flash cache),
|
||||
* with two request buses: bus0 carries instruction fetches, bus1 carries
|
||||
* data accesses (same bus arrangement as the ESP32-C5). The cache is
|
||||
* read-only (no PSRAM, no write-back — see SOC_CACHE_WRITEBACK_SUPPORTED),
|
||||
* so no write-back counters are exposed.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -0,0 +1,459 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/cache_reg.h"
|
||||
#include "soc/cache_struct.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_periph.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4)
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void) type;
|
||||
Cache_Disable_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Suspend_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Invalidate_ICache_All();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
Cache_Freeze_ICache_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (no-op)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
(void)strategy;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (L1 ICache only)
|
||||
*
|
||||
* Starts preload and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
|
||||
* DATA type is no-op.
|
||||
*
|
||||
* @param cache_level level of the cache (CACHE_LL_LEVEL_EXT_MEM or CACHE_LL_LEVEL_ALL)
|
||||
* @param type see `cache_type_t` (only INSTRUCTION and ALL trigger preload)
|
||||
* @param cache_id id of the cache (unused; pass 0)
|
||||
* @param vaddr start virtual address of the preload region
|
||||
* @param size size of the preload region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
Cache_Start_ICache_Preload(vaddr, size, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
if (type == CACHE_TYPE_DATA) {
|
||||
return;
|
||||
}
|
||||
while (Cache_ICache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
//h21 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
|
||||
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
|
||||
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache fail tracer
|
||||
*
|
||||
* @param cache_id cache ID
|
||||
* @param en enable / disable
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
|
||||
{
|
||||
CACHE.trace_ena.l1_cache_trace_ena = en;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
CACHE.l1_cache_acs_fail_int_ena.val |= mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
CACHE.l1_cache_acs_fail_int_clr.val = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return CACHE.l1_cache_acs_fail_int_st.val & mask;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Cache Profile Counter Related
|
||||
-----------------------------------------------------------------------------*/
|
||||
#define CACHE_LL_PROFILE_CNT_ENA_MASK (CACHE_L1_BUS0_CNT_ENA | CACHE_L1_BUS1_CNT_ENA)
|
||||
#define CACHE_LL_PROFILE_CNT_CLR_MASK (CACHE_L1_BUS0_CNT_CLR | CACHE_L1_BUS1_CNT_CLR)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the cache profile counters
|
||||
*
|
||||
* @param ena True to enable, false to disable
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_profile_counter(bool ena)
|
||||
{
|
||||
if (ena) {
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
} else {
|
||||
REG_CLR_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_ENA_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset all cache profile counters to zero
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clear_profile_counter(void)
|
||||
{
|
||||
/* clear bits are write-to-trigger and self-clearing */
|
||||
REG_SET_BIT(CACHE_L1_CACHE_ACS_CNT_CTRL_REG, CACHE_LL_PROFILE_CNT_CLR_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one counter of a cache profile counter unit
|
||||
*
|
||||
* @param unit Unit index, 0 to SOC_CACHE_CNT_UNITS_NUM - 1
|
||||
* @param counter Counter to read
|
||||
* @param[out] value Counter value, only written if the counter exists
|
||||
*
|
||||
* @return True if the unit has this counter, false otherwise
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_get_profile_counter(int unit, cache_profile_counter_t counter, uint32_t *value)
|
||||
{
|
||||
HAL_ASSERT(unit < SOC_CACHE_CNT_UNITS_NUM);
|
||||
uint32_t reg = cache_periph_profile_counter_units[unit].counter_reg[counter];
|
||||
if (reg == 0) {
|
||||
return false;
|
||||
}
|
||||
*value = REG_READ(reg);
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,414 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
(void)vaddr_type;
|
||||
//On ESP32H21, I/D share the same vaddr range
|
||||
return SOC_MMU_IBUS_VADDR_BASE | laddr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
|
||||
return (page_size_code == 0) ? MMU_PAGE_64KB : \
|
||||
(page_size_code == 1) ? MMU_PAGE_32KB : \
|
||||
(page_size_code == 2) ? MMU_PAGE_16KB : \
|
||||
MMU_PAGE_8KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \
|
||||
(size == MMU_PAGE_32KB) ? 1 : \
|
||||
(size == MMU_PAGE_16KB) ? 2 : \
|
||||
(size == MMU_PAGE_8KB) ? 3 : 0;
|
||||
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, uint32_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
/* Note: for ESP32-H21, invert invalid bit for compatible with upper-layer software */
|
||||
mmu_raw_value = mmu_val ^ SOC_MMU_INVALID_MASK;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
|
||||
}
|
||||
/* Note: for ESP32-H21, invert invalid bit for compatible with upper-layer software */
|
||||
ret = mmu_raw_value ^ SOC_MMU_INVALID_MASK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return MMU_TARGET_FLASH0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
|
||||
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-H4 cache profile counter units.
|
||||
*
|
||||
* Single cache level (the flash/PSRAM cache); each core accesses it
|
||||
* through an instruction bus (ibus0/ibus1) and a data bus (dbus0/dbus1),
|
||||
* each with hit/miss/conflict/next-level counters (next-level write
|
||||
* counters on the data buses only).
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-inst-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-inst-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-data-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-data-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,416 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
|
||||
//TODO: [ESP32H4] IDF-12305 inherited from verification branch, need check
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_FLASH_MMU_ID 0
|
||||
#define MMU_LL_PSRAM_MMU_ID 0
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
(void)vaddr_type;
|
||||
//On ESP32C6, I/D share the same vaddr range
|
||||
return SOC_MMU_IBUS_VADDR_BASE | laddr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE);
|
||||
return (page_size_code == 0) ? MMU_PAGE_64KB : \
|
||||
(page_size_code == 1) ? MMU_PAGE_32KB : \
|
||||
(page_size_code == 2) ? MMU_PAGE_16KB : \
|
||||
MMU_PAGE_8KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \
|
||||
(size == MMU_PAGE_32KB) ? 1 : \
|
||||
(size == MMU_PAGE_16KB) ? 2 : \
|
||||
(size == MMU_PAGE_8KB) ? 3 : 0;
|
||||
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
uint32_t mmu_raw_value;
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_val |= SOC_MMU_SENSITIVE;
|
||||
}
|
||||
mmu_val |= (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
|
||||
mmu_raw_value = mmu_val | SOC_MMU_VALID;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t mmu_raw_value;
|
||||
uint32_t ret;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_raw_value &= ~SOC_MMU_SENSITIVE;
|
||||
}
|
||||
if (!(mmu_raw_value & SOC_MMU_VALID)) {
|
||||
return 0;
|
||||
}
|
||||
ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_target_t target = ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_ACCESS_SPIRAM) == 0) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0;
|
||||
return target;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
|
||||
return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
|
||||
if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-P4 cache profile counter units.
|
||||
*
|
||||
* Topology: per-core L1 instruction caches (ibus0/ibus1) and a shared L1
|
||||
* data cache with one port per core (dbus0/dbus1). The L2 (flash/PSRAM)
|
||||
* cache reports all instruction traffic on its ibus0 counters and all data
|
||||
* traffic on its dbus0 counters, regardless of the originating core.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-icache-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-icache-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-dcache-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-dcache-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l2-cache-inst", .level = 2, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = -1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L2_IBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L2_IBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l2-cache-data", .level = 2, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = -1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L2_DBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L2_DBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,578 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_mem_c_reg.h"
|
||||
#include "soc/spi_mem_s_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "esp_fault.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_FLASH_MMU_ID 0
|
||||
#define MMU_LL_PSRAM_MMU_ID 1
|
||||
#define MMU_LL_FLASH_VADDR_TO_PSRAM_VADDR(flash_vaddr) ((flash_vaddr) + SOC_IRAM_FLASH_PSRAM_OFFSET)
|
||||
#define MMU_LL_PSRAM_VADDR_TO_FLASH_VADDR(psram_vaddr) ((psram_vaddr) - SOC_IRAM_FLASH_PSRAM_OFFSET)
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)vaddr_type;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (target == MMU_TARGET_FLASH0) {
|
||||
vaddr_base = SOC_MMU_FLASH_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_PSRAM_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to its target
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return target paddr memory target
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_target_t mmu_ll_vaddr_to_target(uint32_t vaddr)
|
||||
{
|
||||
mmu_target_t target = MMU_TARGET_FLASH0;
|
||||
|
||||
if (SOC_ADDRESS_IN_DRAM_FLASH(vaddr)) {
|
||||
target = MMU_TARGET_FLASH0;
|
||||
} else if (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr)) {
|
||||
target = MMU_TARGET_PSRAM0;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to MMU ID
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_vaddr_to_id(uint32_t vaddr)
|
||||
{
|
||||
uint32_t id = 0;
|
||||
if (vaddr >= SOC_DRAM_FLASH_ADDRESS_LOW && vaddr < SOC_DRAM_FLASH_ADDRESS_HIGH) {
|
||||
id = MMU_LL_FLASH_MMU_ID;
|
||||
} else if (vaddr >= SOC_DRAM_PSRAM_ADDRESS_LOW && vaddr < SOC_DRAM_PSRAM_ADDRESS_HIGH) {
|
||||
id = MMU_LL_PSRAM_MMU_ID;
|
||||
} else {
|
||||
HAL_ASSERT(0);
|
||||
}
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
HAL_ASSERT(size == MMU_PAGE_64KB);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_DRAM_FLASH(vaddr_start) && SOC_ADDRESS_IN_DRAM_FLASH(vaddr_end)) || (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_start) && SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
int max_paddr_page_num = 0;
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
max_paddr_page_num = SOC_MMU_FLASH_MAX_PADDR_PAGE_NUM;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
max_paddr_page_num = SOC_MMU_PSRAM_MAX_PADDR_PAGE_NUM;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * max_paddr_page_num)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * max_paddr_page_num)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * max_paddr_page_num));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t sensitive = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
sensitive = SOC_MMU_FLASH_SENSITIVE;
|
||||
mmu_val |= SOC_MMU_FLASH_VALID;
|
||||
mmu_val |= SOC_MMU_ACCESS_FLASH;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
sensitive = SOC_MMU_PSRAM_SENSITIVE;
|
||||
mmu_val |= SOC_MMU_PSRAM_VALID;
|
||||
mmu_val |= SOC_MMU_ACCESS_PSRAM;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_val |= sensitive;
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
REG_WRITE(content_reg, mmu_val);
|
||||
#if !BOOTLOADER_BUILD
|
||||
// Anti-FI check to confirm the encryption status for PSRAM entry.
|
||||
// This avoids a potential FI attacks to keep PSRAM unencrypted and
|
||||
// hence read out plaintext in execute from PSRAM model.
|
||||
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0) {
|
||||
ESP_FAULT_ASSERT(REG_READ(content_reg) & SOC_MMU_PSRAM_SENSITIVE);
|
||||
} else {
|
||||
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0));
|
||||
}
|
||||
#endif // !BOOTLOADER_BUILD
|
||||
}
|
||||
|
||||
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE
|
||||
/**
|
||||
* Write a PSRAM MMU entry without the SENSITIVE bit, used only for the
|
||||
* carved-out unencrypted region (see CONFIG_SPIRAM_ENC_EXEMPT).
|
||||
*
|
||||
* No anti-FI check: the SENSITIVE bit is intentionally clear, and an FI flip
|
||||
* that sets it would force decryption of plaintext data (garbage, fails safe).
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry_no_enc(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val)
|
||||
{
|
||||
HAL_ASSERT(mmu_id == MMU_LL_PSRAM_MMU_ID);
|
||||
|
||||
mmu_val |= SOC_MMU_PSRAM_VALID;
|
||||
mmu_val |= SOC_MMU_ACCESS_PSRAM;
|
||||
|
||||
REG_WRITE(SPI_MEM_S_MMU_ITEM_INDEX_REG, entry_id);
|
||||
REG_WRITE(SPI_MEM_S_MMU_ITEM_CONTENT_REG, mmu_val);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t mmu_val = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
mmu_val = REG_READ(content_reg);
|
||||
|
||||
return mmu_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t invalid_mask = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
invalid_mask = SOC_MMU_FLASH_INVALID;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
invalid_mask = SOC_MMU_PSRAM_INVALID;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
REG_WRITE(content_reg, invalid_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t mmu_raw_value = 0;
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t valid_mask = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
valid_mask = SOC_MMU_FLASH_VALID;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
valid_mask = SOC_MMU_PSRAM_VALID;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
mmu_raw_value = REG_READ(content_reg);
|
||||
|
||||
bool is_valid = false;
|
||||
if (mmu_raw_value & valid_mask) {
|
||||
is_valid = true;
|
||||
}
|
||||
|
||||
return is_valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)entry_id;
|
||||
mmu_target_t target = MMU_TARGET_FLASH0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
target = MMU_TARGET_FLASH0;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
target = MMU_TARGET_PSRAM0;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
uint32_t paddr_base = 0;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id);
|
||||
paddr_base = (REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & SOC_MMU_FLASH_VALID_VAL_MASK) << shift_code;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
REG_WRITE(SPI_MEM_S_MMU_ITEM_INDEX_REG, entry_id);
|
||||
paddr_base = (REG_READ(SPI_MEM_S_MMU_ITEM_CONTENT_REG) & SOC_MMU_PSRAM_VALID_VAL_MASK) << shift_code;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return paddr_base;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t valid_val_mask = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
valid_val_mask = SOC_MMU_FLASH_VALID_VAL_MASK;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
valid_val_mask = SOC_MMU_PSRAM_VALID_VAL_MASK;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(index_reg, i);
|
||||
if ((REG_READ(content_reg) & valid_val_mask) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, (mmu_id == MMU_LL_FLASH_MMU_ID) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,678 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32s2/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
|
||||
|
||||
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
|
||||
#define CACHE_LL_L1_DCACHE_AUTOLOAD (1<<0)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if ICache auto preload is enabled or not
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_icache_autoload_enabled(void)
|
||||
{
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DCache auto preload is enabled or not
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_dcache_autoload_enabled(void)
|
||||
{
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
enabled = cache_ll_l1_is_icache_autoload_enabled();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
enabled = cache_ll_l1_is_dcache_autoload_enabled();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
enabled = cache_ll_l1_is_icache_autoload_enabled() && cache_ll_l1_is_dcache_autoload_enabled();
|
||||
break;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (no-op)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
(void)strategy;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache
|
||||
*
|
||||
* @param cache_level level of the cache (must be CACHE_LL_LEVEL_EXT_MEM)
|
||||
* @param type see `cache_type_t` (INSTRUCTION, DATA, or ALL)
|
||||
* @param cache_id id of the cache (unused on S2; pass 0 or CACHE_LL_ID_ALL)
|
||||
* @param vaddr start virtual address of the preload region
|
||||
* @param size size of the preload region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
Cache_Start_ICache_Preload(vaddr, size, order);
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
Cache_Start_DCache_Preload(vaddr, size, order);
|
||||
break;
|
||||
case CACHE_TYPE_ALL:
|
||||
default:
|
||||
Cache_Start_ICache_Preload(vaddr, size, order);
|
||||
Cache_Start_DCache_Preload(vaddr, size, order);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
while (Cache_ICache_Preload_Done() == 0) {
|
||||
}
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
while (Cache_DCache_Preload_Done() == 0) {
|
||||
}
|
||||
break;
|
||||
case CACHE_TYPE_ALL:
|
||||
default:
|
||||
while (Cache_ICache_Preload_Done() == 0) {
|
||||
}
|
||||
while (Cache_DCache_Preload_Done() == 0) {
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ICache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_icache(void)
|
||||
{
|
||||
Cache_Disable_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DCache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_dcache(void)
|
||||
{
|
||||
Cache_Disable_DCache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_disable_icache();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_disable_dcache();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_disable_icache();
|
||||
cache_ll_l1_disable_dcache();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable ICache
|
||||
*
|
||||
* @param inst_autoload_en ICache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_enable_icache(bool inst_autoload_en)
|
||||
{
|
||||
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DCache
|
||||
*
|
||||
* @param data_autoload_en DCache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_enable_dcache(bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_enable_icache(inst_autoload_en);
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_enable_dcache(data_autoload_en);
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_enable_icache(inst_autoload_en);
|
||||
cache_ll_l1_enable_dcache(data_autoload_en);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend ICache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_suspend_icache(void)
|
||||
{
|
||||
Cache_Suspend_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend DCache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_suspend_dcache(void)
|
||||
{
|
||||
Cache_Suspend_DCache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_suspend_icache();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_suspend_dcache();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_suspend_icache();
|
||||
cache_ll_l1_suspend_dcache();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume ICache
|
||||
*
|
||||
* @param inst_autoload_en ICache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_resume_icache(bool inst_autoload_en)
|
||||
{
|
||||
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume DCache
|
||||
*
|
||||
* @param data_autoload_en DCache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_resume_dcache(bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_resume_icache(inst_autoload_en);
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_resume_dcache(data_autoload_en);
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_resume_icache(inst_autoload_en);
|
||||
cache_ll_l1_resume_dcache(data_autoload_en);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if ICache is enabled or not
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
|
||||
bool enabled;
|
||||
enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE);
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DCache is enabled or not
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_dcache_enabled(uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
|
||||
bool enabled;
|
||||
enabled = REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE);
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if ICache or DCache or both is enabled or not
|
||||
*
|
||||
* @param type see `cache_type_t`
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
|
||||
{
|
||||
bool enabled = false;
|
||||
switch (type) {
|
||||
case CACHE_TYPE_DATA:
|
||||
enabled = cache_ll_l1_is_dcache_enabled(0);
|
||||
break;
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
enabled = cache_ll_l1_is_icache_enabled(0);
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
enabled = cache_ll_l1_is_dcache_enabled(0) && cache_ll_l1_is_icache_enabled(0);
|
||||
break;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_DATA:
|
||||
Cache_Invalidate_DCache_All();
|
||||
break;
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
Cache_Invalidate_ICache_All();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
Cache_Invalidate_ICache_All();
|
||||
Cache_Invalidate_DCache_All();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writeback cache supported addr
|
||||
*
|
||||
* Writeback a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be written back
|
||||
* @param size size of the region to be written back
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_WriteBack_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ICache line size, in bytes
|
||||
*
|
||||
* @return ICache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_l1_icache_get_line_size(void)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DCache line size, in bytes
|
||||
*
|
||||
* @return DCache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_l1_dcache_get_line_size(void)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_DCache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
size = cache_ll_l1_icache_get_line_size();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
size = cache_ll_l1_dcache_get_line_size();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
|
||||
} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DRAM1_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS2);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else if (vaddr_start >= SOC_DROM0_ADDRESS_LOW) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
|
||||
mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
(void)bus_id;
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
|
||||
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
|
||||
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param bus_id bus ID
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
(void)bus_id;
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
|
||||
REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
|
||||
REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= ((vaddr_start >= SOC_DROM0_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH));
|
||||
valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM1_ADDRESS_HIGH));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get cache debug status 0
|
||||
*
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_dbg_status0(void)
|
||||
{
|
||||
return REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get cache debug status 1
|
||||
*
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_dbg_status1(void)
|
||||
{
|
||||
return REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,384 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - 0x10000)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (192 - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (vaddr_type == MMU_VADDR_DATA) {
|
||||
vaddr_base = SOC_MMU_DBUS_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_IBUS_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
//On esp32s2, MMU Page size is always 64KB
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*
|
||||
* @note On esp32s2, only supports `MMU_PAGE_64KB`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
HAL_ASSERT(size == MMU_PAGE_64KB);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
bool valid = false;
|
||||
|
||||
if (type & MMU_VADDR_DATA) {
|
||||
valid |= ((vaddr_start >= SOC_DROM0_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH));
|
||||
}
|
||||
|
||||
if (type & MMU_VADDR_INSTRUCTION) {
|
||||
valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM1_ADDRESS_HIGH));
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t offset = 0;
|
||||
|
||||
if (SOC_ADDRESS_IN_DROM0(vaddr)) {
|
||||
offset = PRO_CACHE_IBUS2_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)) {
|
||||
offset = PRO_CACHE_IBUS0_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_IRAM1(vaddr)) {
|
||||
offset = PRO_CACHE_IBUS1_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_DPORT_CACHE(vaddr)) {
|
||||
offset = PRO_CACHE_DBUS2_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_DRAM1(vaddr)) {
|
||||
offset = PRO_CACHE_DBUS1_MMU_START / 4;
|
||||
} else if (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)) {
|
||||
offset = PRO_CACHE_DBUS0_MMU_START / 4;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return offset + ((vaddr & SOC_MMU_VADDR_MASK) >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
return paddr >> 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
uint32_t target_code = (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | SOC_MMU_VALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id));
|
||||
|
||||
if ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_ACCESS_FLASH) {
|
||||
return MMU_TARGET_FLASH0;
|
||||
} else {
|
||||
return MMU_TARGET_PSRAM0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
|
||||
return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
|
||||
uint32_t vaddr_base = 0;
|
||||
if (entry_id < 0x40) {
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 0x40 && entry_id < 0x80) {
|
||||
if (type != MMU_VADDR_INSTRUCTION) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x40;
|
||||
vaddr_base = 0x40000000;
|
||||
} else if (entry_id >= 0x80 && entry_id < 0xC0) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x80;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else if (entry_id >= 0xC0 && entry_id < 0x100) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0xC0;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else if (entry_id >= 0x100 && entry_id < 0x140) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x100;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else if (entry_id >= 0x140 && entry_id < 0x180) {
|
||||
if (type != MMU_VADDR_DATA) {
|
||||
return 0;
|
||||
}
|
||||
entry_id -= 0x140;
|
||||
vaddr_base = 0x3f000000;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return vaddr_base + (entry_id << 16);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,957 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for Cache register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32s3/rom/cache.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
|
||||
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
|
||||
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_DC_INT (1<<3)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1)
|
||||
#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0)
|
||||
|
||||
#define CACHE_LL_L1_ILG_EVENT_MASK (0x3f)
|
||||
#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5)
|
||||
#define CACHE_LL_L1_ILG_EVENT_DCACHE_WRITE_FLASH (1<<4)
|
||||
#define CACHE_LL_L1_ILG_EVENT_DCACHE_PRELOAD_OP_FAULT (1<<3)
|
||||
#define CACHE_LL_L1_ILG_EVENT_DCACHE_SYNC_OP_FAULT (1<<2)
|
||||
#define CACHE_LL_L1_ILG_EVENT_ICACHE_PRELOAD_OP_FAULT (1<<1)
|
||||
#define CACHE_LL_L1_ILG_EVENT_ICACHE_SYNC_OP_FAULT (1<<0)
|
||||
|
||||
#define CACHE_LL_ID_ALL 2 //All of the caches in a type and level, make this value greater than any id
|
||||
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
|
||||
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
|
||||
#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
|
||||
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
|
||||
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<2)
|
||||
#define CACHE_LL_L1_DCACHE_AUTOLOAD (1<<2)
|
||||
|
||||
/**
|
||||
* @brief Preload strategy
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
|
||||
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
|
||||
CACHE_LL_PRELOAD_ARBITRARY = 2,
|
||||
} cache_ll_preload_strategy_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize the cache clock
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_clk_init(void)
|
||||
{
|
||||
//for compatibility
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if ICache auto preload is enabled or not
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_icache_autoload_enabled(void)
|
||||
{
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(EXTMEM_ICACHE_AUTOLOAD_CTRL_REG, EXTMEM_ICACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DCache auto preload is enabled or not
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_dcache_autoload_enabled(void)
|
||||
{
|
||||
bool enabled = false;
|
||||
if (REG_GET_BIT(EXTMEM_DCACHE_AUTOLOAD_CTRL_REG, EXTMEM_DCACHE_AUTOLOAD_ENA)) {
|
||||
enabled = true;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Cache auto preload is enabled or not.
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
bool enabled = false;
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
enabled = cache_ll_l1_is_icache_autoload_enabled();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
enabled = cache_ll_l1_is_dcache_autoload_enabled();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
enabled = cache_ll_l1_is_icache_autoload_enabled() && cache_ll_l1_is_dcache_autoload_enabled();
|
||||
break;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Preload (manual preload only; no autoload, via ROM API)
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Check if L1 ICache preload is in progress
|
||||
*
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
|
||||
* @return true: preload in progress; false: idle
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_icache_preload_busy(uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
return Cache_ICache_Preload_Done() == 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if L1 DCache preload is in progress
|
||||
*
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
|
||||
* @return true: preload in progress; false: idle
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_dcache_preload_busy(uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
return Cache_DCache_Preload_Done() == 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set L1 ICache preload address and start preload (ROM: suspends autoload)
|
||||
*
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
|
||||
* @param vaddr start virtual address for preload
|
||||
* @param size_bytes size of region in bytes
|
||||
* @param order preload order
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_icache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size_bytes, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
Cache_Start_ICache_Preload(vaddr, size_bytes, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set L1 DCache preload address and start preload (ROM: suspends autoload)
|
||||
*
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
|
||||
* @param vaddr start virtual address for preload
|
||||
* @param size_bytes size of region in bytes
|
||||
* @param order preload order
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_dcache_preload(uint32_t cache_id, uint32_t vaddr, uint32_t size_bytes, cache_preload_order_t order)
|
||||
{
|
||||
(void)cache_id;
|
||||
Cache_Start_DCache_Preload(vaddr, size_bytes, order);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until L1 ICache preload is done
|
||||
*
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_icache_preload_wait_done(uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
while (Cache_ICache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until L1 DCache preload is done
|
||||
*
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL on S3)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_dcache_preload_wait_done(uint32_t cache_id)
|
||||
{
|
||||
(void)cache_id;
|
||||
while (Cache_DCache_Preload_Done() == 0) {
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the preload strategy (no-op)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
|
||||
{
|
||||
(void)cache_level;
|
||||
(void)type;
|
||||
(void)cache_id;
|
||||
(void)strategy;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Preload cache (L1 only)
|
||||
*
|
||||
* Starts preload for the given region and does not wait. Use
|
||||
* cache_ll_l1_*_preload_wait_done() to wait for completion.
|
||||
*
|
||||
* @param cache_level level of the cache (must be 1)
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL)
|
||||
* @param vaddr start virtual address for preload
|
||||
* @param size size of region in bytes
|
||||
* @param order preload order, see `cache_preload_order_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, cache_preload_order_t order)
|
||||
{
|
||||
HAL_ASSERT(cache_level == 1);
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
|
||||
break;
|
||||
case CACHE_TYPE_ALL:
|
||||
default:
|
||||
cache_ll_l1_icache_preload(cache_id, vaddr, size, order);
|
||||
cache_ll_l1_dcache_preload(cache_id, vaddr, size, order);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload is done (L1 only)
|
||||
*
|
||||
* @param cache_level level of the cache (must be 1)
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache (0 or CACHE_LL_ID_ALL)
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_level == 1);
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_icache_preload_wait_done(cache_id);
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_dcache_preload_wait_done(cache_id);
|
||||
break;
|
||||
case CACHE_TYPE_ALL:
|
||||
default:
|
||||
cache_ll_l1_icache_preload_wait_done(cache_id);
|
||||
cache_ll_l1_dcache_preload_wait_done(cache_id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ICache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_icache(void)
|
||||
{
|
||||
Cache_Disable_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable DCache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_dcache(void)
|
||||
{
|
||||
Cache_Disable_DCache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_disable_icache();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_disable_dcache();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_disable_icache();
|
||||
cache_ll_l1_disable_dcache();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable ICache
|
||||
*
|
||||
* @param inst_autoload_en ICache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_enable_icache(bool inst_autoload_en)
|
||||
{
|
||||
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable DCache
|
||||
*
|
||||
* @param data_autoload_en DCache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_enable_dcache(bool data_autoload_en)
|
||||
{
|
||||
Cache_Enable_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_enable_icache(inst_autoload_en);
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_enable_dcache(data_autoload_en);
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_enable_icache(inst_autoload_en);
|
||||
cache_ll_l1_enable_dcache(data_autoload_en);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend ICache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_suspend_icache(void)
|
||||
{
|
||||
Cache_Suspend_ICache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend DCache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_suspend_dcache(void)
|
||||
{
|
||||
Cache_Suspend_DCache();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_suspend_icache();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_suspend_dcache();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_suspend_icache();
|
||||
cache_ll_l1_suspend_dcache();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume ICache
|
||||
*
|
||||
* @param inst_autoload_en ICache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_resume_icache(bool inst_autoload_en)
|
||||
{
|
||||
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume DCache
|
||||
*
|
||||
* @param data_autoload_en DCache auto preload enabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_resume_dcache(bool data_autoload_en)
|
||||
{
|
||||
Cache_Resume_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param data_autoload_en data autoload enabled or not
|
||||
* @param inst_autoload_en inst autoload enabled or not
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_resume_icache(inst_autoload_en);
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_resume_dcache(data_autoload_en);
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_resume_icache(inst_autoload_en);
|
||||
cache_ll_l1_resume_dcache(data_autoload_en);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if ICache is enabled or not
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
return REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DCache is enabled or not
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_l1_is_dcache_enabled(uint32_t cache_id)
|
||||
{
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
return REG_GET_BIT(EXTMEM_DCACHE_CTRL_REG, EXTMEM_DCACHE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if ICache or DCache or both is enabled or not
|
||||
*
|
||||
* @param type see `cache_type_t`
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
|
||||
{
|
||||
bool enabled = false;
|
||||
switch (type) {
|
||||
case CACHE_TYPE_DATA:
|
||||
enabled = cache_ll_l1_is_dcache_enabled(0);
|
||||
break;
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
enabled = cache_ll_l1_is_icache_enabled(0);
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
enabled = cache_ll_l1_is_dcache_enabled(0) && cache_ll_l1_is_icache_enabled(0);
|
||||
break;
|
||||
}
|
||||
return enabled;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate cache supported addr
|
||||
*
|
||||
* Invalidate a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be invalidated
|
||||
* @param size size of the region to be invalidated
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_Invalidate_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Invalidate all
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_DATA:
|
||||
Cache_Invalidate_DCache_All();
|
||||
break;
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
Cache_Invalidate_ICache_All();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
Cache_Invalidate_ICache_All();
|
||||
Cache_Invalidate_DCache_All();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writeback cache supported addr
|
||||
*
|
||||
* Writeback a cache item
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
* @param vaddr start address of the region to be written back
|
||||
* @param size size of the region to be written back
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
|
||||
{
|
||||
Cache_WriteBack_Addr(vaddr, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze ICache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_freeze_icache(void)
|
||||
{
|
||||
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze DCache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_freeze_dcache(void)
|
||||
{
|
||||
Cache_Freeze_DCache_Enable(CACHE_FREEZE_ACK_BUSY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_freeze_icache();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_freeze_dcache();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_freeze_icache();
|
||||
cache_ll_l1_freeze_dcache();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze ICache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_unfreeze_icache(void)
|
||||
{
|
||||
Cache_Freeze_ICache_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze DCache
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_unfreeze_dcache(void)
|
||||
{
|
||||
Cache_Freeze_DCache_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unfreeze Cache
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
cache_ll_l1_unfreeze_icache();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
cache_ll_l1_unfreeze_dcache();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
cache_ll_l1_unfreeze_icache();
|
||||
cache_ll_l1_unfreeze_dcache();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ICache line size, in bytes
|
||||
*
|
||||
* @return ICache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_l1_icache_get_line_size(void)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_ICache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get DCache line size, in bytes
|
||||
*
|
||||
* @return DCache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_l1_dcache_get_line_size(void)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
size = Cache_Get_DCache_Line_Size();
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache line size, in bytes
|
||||
*
|
||||
* @param cache_level level of the cache
|
||||
* @param type see `cache_type_t`
|
||||
* @param cache_id id of the cache in this type and level
|
||||
*
|
||||
* @return Cache line size, in bytes
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
|
||||
{
|
||||
uint32_t size = 0;
|
||||
switch (type) {
|
||||
case CACHE_TYPE_INSTRUCTION:
|
||||
size = cache_ll_l1_icache_get_line_size();
|
||||
break;
|
||||
case CACHE_TYPE_DATA:
|
||||
size = cache_ll_l1_dcache_get_line_size();
|
||||
break;
|
||||
default: //CACHE_TYPE_ALL
|
||||
HAL_ASSERT(false);
|
||||
break;
|
||||
}
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the buses of a particular cache that are mapped to a virtual address range
|
||||
*
|
||||
* External virtual address can only be accessed when the involved cache buses are enabled.
|
||||
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0); //Both cores have their own IBUS0
|
||||
} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
|
||||
mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0); //Both cores have their own DBUS0
|
||||
} else {
|
||||
HAL_ASSERT(0); //Out of region
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the Cache Buses
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param mask To know which buses should be enabled
|
||||
*/
|
||||
#if !BOOTLOADER_BUILD
|
||||
__attribute__((always_inline))
|
||||
#endif
|
||||
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
if (bus_id == 0) {
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
|
||||
} else {
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0);
|
||||
}
|
||||
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
if (bus_id == 1) {
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0);
|
||||
} else {
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0);
|
||||
}
|
||||
REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns enabled buses for a given core
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
*
|
||||
* @return State of enabled buses
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
|
||||
{
|
||||
cache_bus_mask_t mask = (cache_bus_mask_t)0;
|
||||
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
|
||||
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
|
||||
uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG);
|
||||
if (cache_id == 0) {
|
||||
mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0));
|
||||
} else {
|
||||
mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0));
|
||||
}
|
||||
|
||||
uint32_t dbus_mask = REG_READ(EXTMEM_DCACHE_CTRL1_REG);
|
||||
if (cache_id == 1) {
|
||||
mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0));
|
||||
} else {
|
||||
mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0));
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the Cache Buses
|
||||
*
|
||||
* @param cache_id cache ID (when l1 cache is per core)
|
||||
* @param mask To know which buses should be disabled
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
|
||||
{
|
||||
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
||||
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
|
||||
|
||||
uint32_t ibus_mask = 0;
|
||||
if (bus_id == 0) {
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0);
|
||||
} else {
|
||||
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0);
|
||||
}
|
||||
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
|
||||
|
||||
uint32_t dbus_mask = 0;
|
||||
if (bus_id == 1) {
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0);
|
||||
} else {
|
||||
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0);
|
||||
}
|
||||
REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
||||
{
|
||||
bool valid = false;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
|
||||
if (valid) {
|
||||
*out_level = 1;
|
||||
*out_id = 0;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Interrupt
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Enable Cache access error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
if (cache_id == 0) {
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask);
|
||||
} else {
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG, mask);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
if (cache_id == 0) {
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask);
|
||||
} else {
|
||||
SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG, mask);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache access error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
if (cache_id == 0) {
|
||||
return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask);
|
||||
} else {
|
||||
return GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, mask);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Cache illegal error interrupt
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Cache illegal error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*/
|
||||
static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Cache illegal error interrupt status
|
||||
*
|
||||
* @param cache_id Cache ID
|
||||
* @param mask Interrupt mask
|
||||
*
|
||||
* @return Status mask
|
||||
*/
|
||||
static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask)
|
||||
{
|
||||
return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read vaddr that caused acs dbus reject error
|
||||
*
|
||||
* @param cache_id cache id to get vaddr from
|
||||
*
|
||||
* @return vaddr that cause the acs dbus reject error
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t cache_ll_get_acs_dbus_reject_vaddr(uint32_t cache_id)
|
||||
{
|
||||
if (cache_id == 0) {
|
||||
return REG_READ(EXTMEM_CORE0_DBUS_REJECT_VADDR_REG);
|
||||
} else {
|
||||
return REG_READ(EXTMEM_CORE1_DBUS_REJECT_VADDR_REG);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,325 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_types.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - 0x10000)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target, not used
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (vaddr_type == MMU_VADDR_DATA) {
|
||||
vaddr_base = SOC_MMU_DBUS_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_IBUS_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
//On esp32s3, MMU Page size is always 64KB
|
||||
(void)mmu_id;
|
||||
return MMU_PAGE_64KB;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*
|
||||
* @note On esp32s3, only supports `MMU_PAGE_64KB`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
HAL_ASSERT(size == MMU_PAGE_64KB);
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
bool valid = false;
|
||||
|
||||
if (type & MMU_VADDR_INSTRUCTION) {
|
||||
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
if (type & MMU_VADDR_DATA) {
|
||||
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
(void)mmu_id;
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)target;
|
||||
return paddr >> 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
uint32_t target_code = (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | SOC_MMU_VALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
bool target_code = (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_TYPE;
|
||||
return (target_code == SOC_MMU_ACCESS_FLASH) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)mmu_id;
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << 16;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
(void)mmu_id;
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
uint32_t laddr = entry_id << 16;
|
||||
|
||||
/**
|
||||
* For `mmu_ll_laddr_to_vaddr`, target is for compatibility on this chip.
|
||||
* Here we just pass MMU_TARGET_FLASH0 to get vaddr
|
||||
*/
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-S31 cache profile counter units.
|
||||
*
|
||||
* The register layout matches the ESP32-P4: per-bus hit/miss/conflict and
|
||||
* next-level read/write counters, with the same counter semantics. There
|
||||
* is a single cache level (the flash/PSRAM cache, 64-byte lines); each
|
||||
* core accesses it through an instruction bus (ibus0/ibus1) and a data
|
||||
* bus (dbus0/dbus1). Only the CPU request buses are exposed here.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-inst-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-inst-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-data-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-data-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,610 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for MMU register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/spi_mem_c_reg.h"
|
||||
#include "soc/spi_mem_s_reg.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_types.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MMU_LL_FLASH_MMU_ID 0
|
||||
#define MMU_LL_PSRAM_MMU_ID 1
|
||||
#define MMU_LL_FLASH_VADDR_TO_PSRAM_VADDR(flash_vaddr) ((flash_vaddr) + SOC_IRAM_FLASH_PSRAM_OFFSET)
|
||||
#define MMU_LL_PSRAM_VADDR_TO_FLASH_VADDR(psram_vaddr) ((psram_vaddr) - SOC_IRAM_FLASH_PSRAM_OFFSET)
|
||||
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
|
||||
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to linear address
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return linear address
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
|
||||
{
|
||||
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU linear address to virtual address
|
||||
*
|
||||
* @param laddr linear address
|
||||
* @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
* @param target virtual address aimed physical memory target
|
||||
*
|
||||
* @return virtual address
|
||||
*/
|
||||
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
|
||||
{
|
||||
(void)vaddr_type;
|
||||
uint32_t vaddr_base = 0;
|
||||
if (target == MMU_TARGET_FLASH0) {
|
||||
vaddr_base = SOC_MMU_FLASH_VADDR_BASE;
|
||||
} else {
|
||||
vaddr_base = SOC_MMU_PSRAM_VADDR_BASE;
|
||||
}
|
||||
|
||||
return vaddr_base | laddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to its target
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return target paddr memory target
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_target_t mmu_ll_vaddr_to_target(uint32_t vaddr)
|
||||
{
|
||||
mmu_target_t target = MMU_TARGET_FLASH0;
|
||||
|
||||
if (SOC_ADDRESS_IN_DRAM_FLASH(vaddr)) {
|
||||
target = MMU_TARGET_FLASH0;
|
||||
} else if (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr)) {
|
||||
target = MMU_TARGET_PSRAM0;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU virtual address to MMU ID
|
||||
*
|
||||
* @param vaddr virtual address
|
||||
*
|
||||
* @return MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_vaddr_to_id(uint32_t vaddr)
|
||||
{
|
||||
uint32_t id = 0;
|
||||
if (vaddr >= SOC_DRAM_FLASH_ADDRESS_LOW && vaddr < SOC_DRAM_FLASH_ADDRESS_HIGH) {
|
||||
id = MMU_LL_FLASH_MMU_ID;
|
||||
} else if (vaddr >= SOC_DRAM_PSRAM_ADDRESS_LOW && vaddr < SOC_DRAM_PSRAM_ADDRESS_HIGH) {
|
||||
id = MMU_LL_PSRAM_MMU_ID;
|
||||
} else {
|
||||
HAL_ASSERT(0);
|
||||
}
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
|
||||
{
|
||||
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
|
||||
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
|
||||
cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
|
||||
return (cnt == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get MMU page size
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*
|
||||
* @return MMU page size code
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
|
||||
{
|
||||
uint32_t page_size_code = 0;
|
||||
mmu_page_size_t page_size = MMU_PAGE_64KB;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
page_size_code = REG_GET_FIELD(SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MMU_PAGE_SIZE);
|
||||
page_size = (page_size_code == 0) ? MMU_PAGE_256KB : \
|
||||
(page_size_code == 1) ? MMU_PAGE_128KB : \
|
||||
(page_size_code == 2) ? MMU_PAGE_64KB : \
|
||||
MMU_PAGE_32KB;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
page_size_code = REG_GET_FIELD(SPI_MEM_S_MMU_POWER_CTRL_REG, SPI_MMU_PAGE_SIZE);
|
||||
page_size = (page_size_code == 0) ? MMU_PAGE_64KB : \
|
||||
(page_size_code == 1) ? MMU_PAGE_32KB : \
|
||||
(page_size_code == 2) ? MMU_PAGE_16KB : \
|
||||
MMU_PAGE_8KB;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return page_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU page size
|
||||
*
|
||||
* @param size MMU page size
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
|
||||
{
|
||||
uint8_t reg_val = 0;
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
reg_val = (size == MMU_PAGE_256KB) ? 0 : \
|
||||
(size == MMU_PAGE_128KB) ? 1 : \
|
||||
(size == MMU_PAGE_64KB) ? 2 : \
|
||||
(size == MMU_PAGE_32KB) ? 3 : 0;
|
||||
REG_SET_FIELD(SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MMU_PAGE_SIZE, reg_val);
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
reg_val = (size == MMU_PAGE_64KB) ? 0 : \
|
||||
(size == MMU_PAGE_32KB) ? 1 : \
|
||||
(size == MMU_PAGE_16KB) ? 2 : \
|
||||
(size == MMU_PAGE_8KB) ? 3 : 0;
|
||||
REG_SET_FIELD(SPI_MEM_S_MMU_POWER_CTRL_REG, SPI_MMU_PAGE_SIZE, reg_val);
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the external memory vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
(void)mmu_id;
|
||||
(void)type;
|
||||
uint32_t vaddr_end = vaddr_start + len - 1;
|
||||
return (SOC_ADDRESS_IN_DRAM_FLASH(vaddr_start) && SOC_ADDRESS_IN_DRAM_FLASH(vaddr_end)) || (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_start) && SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_end));
|
||||
}
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
int max_paddr_page_num = 0;
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
max_paddr_page_num = SOC_MMU_FLASH_MAX_PADDR_PAGE_NUM;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
max_paddr_page_num = SOC_MMU_PSRAM_MAX_PADDR_PAGE_NUM;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * max_paddr_page_num)) &&
|
||||
(len < (mmu_ll_get_page_size(mmu_id) * max_paddr_page_num)) &&
|
||||
((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * max_paddr_page_num));
|
||||
}
|
||||
|
||||
/**
|
||||
* To get the MMU table entry id to be mapped
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address to be mapped
|
||||
*
|
||||
* @return
|
||||
* MMU table entry id
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_256KB:
|
||||
shift_code = 18;
|
||||
break;
|
||||
case MMU_PAGE_128KB:
|
||||
shift_code = 17;
|
||||
break;
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
|
||||
}
|
||||
|
||||
/**
|
||||
* Format the paddr to be mappable
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address to be mapped
|
||||
* @param target paddr memory target, not used
|
||||
*
|
||||
* @return
|
||||
* mmu_val - paddr in MMU table supported format
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
|
||||
{
|
||||
(void)target;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_256KB:
|
||||
shift_code = 18;
|
||||
break;
|
||||
case MMU_PAGE_128KB:
|
||||
shift_code = 17;
|
||||
break;
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return paddr >> shift_code;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write to the MMU table to map the virtual memory and the physical memory
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be set into an MMU entry, for physical address
|
||||
* @param target MMU target physical memory.
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t sensitive = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
sensitive = SOC_MMU_FLASH_SENSITIVE;
|
||||
mmu_val |= SOC_MMU_FLASH_VALID;
|
||||
mmu_val |= SOC_MMU_ACCESS_FLASH;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
sensitive = SOC_MMU_PSRAM_SENSITIVE;
|
||||
mmu_val |= SOC_MMU_PSRAM_VALID;
|
||||
mmu_val |= SOC_MMU_ACCESS_PSRAM;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
if (mmu_ll_cache_encryption_enabled()) {
|
||||
mmu_val |= sensitive;
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
REG_WRITE(content_reg, mmu_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* Read the raw value from MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param mmu_val Value to be read from MMU table
|
||||
*/
|
||||
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t mmu_val = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
mmu_val = REG_READ(content_reg);
|
||||
|
||||
return mmu_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set MMU table entry as invalid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t invalid_mask = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
invalid_mask = SOC_MMU_FLASH_INVALID;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
invalid_mask = SOC_MMU_PSRAM_INVALID;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
REG_WRITE(content_reg, invalid_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Unmap all the items in the MMU table
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
|
||||
{
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
mmu_ll_set_entry_invalid(mmu_id, i);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Check MMU table entry value is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return True for MMU entry is valid; False for invalid
|
||||
*/
|
||||
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
uint32_t mmu_raw_value = 0;
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t valid_mask = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
valid_mask = SOC_MMU_FLASH_VALID;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
valid_mask = SOC_MMU_PSRAM_VALID;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
REG_WRITE(index_reg, entry_id);
|
||||
mmu_raw_value = REG_READ(content_reg);
|
||||
|
||||
bool is_valid = false;
|
||||
if (mmu_raw_value & valid_mask) {
|
||||
is_valid = true;
|
||||
}
|
||||
|
||||
return is_valid;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the MMU table entry target
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return Target, see `mmu_target_t`
|
||||
*/
|
||||
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
(void)entry_id;
|
||||
mmu_target_t target = MMU_TARGET_FLASH0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
target = MMU_TARGET_FLASH0;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
target = MMU_TARGET_PSRAM0;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to paddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
*
|
||||
* @return paddr base
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
|
||||
{
|
||||
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
|
||||
|
||||
uint32_t paddr_base = 0;
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id);
|
||||
paddr_base = (REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & SOC_MMU_FLASH_VALID_VAL_MASK) << shift_code;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
REG_WRITE(SPI_MEM_S_MMU_ITEM_INDEX_REG, entry_id);
|
||||
paddr_base = (REG_READ(SPI_MEM_S_MMU_ITEM_CONTENT_REG) & SOC_MMU_PSRAM_VALID_VAL_MASK) << shift_code;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
return paddr_base;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the MMU table entry ID based on table map value
|
||||
* @note This function can only find the first match entry ID. However it is possible that a physical address
|
||||
* is mapped to multiple virtual addresses
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mmu_val map value to be read from MMU table standing for paddr
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
*
|
||||
* @return MMU entry ID, -1 for invalid
|
||||
*/
|
||||
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
|
||||
{
|
||||
uint32_t index_reg = 0;
|
||||
uint32_t content_reg = 0;
|
||||
uint32_t valid_val_mask = 0;
|
||||
|
||||
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
|
||||
index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
|
||||
valid_val_mask = SOC_MMU_FLASH_VALID_VAL_MASK;
|
||||
} else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
|
||||
index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
|
||||
content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
|
||||
valid_val_mask = SOC_MMU_PSRAM_VALID_VAL_MASK;
|
||||
} else {
|
||||
HAL_ASSERT(false);
|
||||
}
|
||||
|
||||
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
|
||||
if (mmu_ll_check_entry_valid(mmu_id, i)) {
|
||||
if (mmu_ll_get_entry_target(mmu_id, i) == target) {
|
||||
REG_WRITE(index_reg, i);
|
||||
if ((REG_READ(content_reg) & valid_val_mask) == mmu_val) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert MMU entry ID to vaddr base
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param entry_id MMU entry ID
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*/
|
||||
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
case MMU_PAGE_8KB:
|
||||
shift_code = 13;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
uint32_t laddr = entry_id << shift_code;
|
||||
return mmu_ll_laddr_to_vaddr(laddr, type, (mmu_id == MMU_LL_FLASH_MMU_ID) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a PSRAM MMU entry without the SENSITIVE bit, used only for the
|
||||
* carved-out unencrypted region (see CONFIG_SPIRAM_ENC_EXEMPT).
|
||||
*
|
||||
* No anti-FI check: the SENSITIVE bit is intentionally clear, and an FI flip
|
||||
* that sets it would force decryption of plaintext data (garbage, fails safe).
|
||||
*/
|
||||
__attribute__((always_inline)) static inline void mmu_ll_write_entry_no_enc(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val)
|
||||
{
|
||||
HAL_ASSERT(mmu_id == MMU_LL_PSRAM_MMU_ID);
|
||||
|
||||
mmu_val |= SOC_MMU_PSRAM_VALID;
|
||||
mmu_val |= SOC_MMU_ACCESS_PSRAM;
|
||||
|
||||
REG_WRITE(SPI_MEM_S_MMU_ITEM_INDEX_REG, entry_id);
|
||||
REG_WRITE(SPI_MEM_S_MMU_ITEM_CONTENT_REG, mmu_val);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,185 @@
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/cache_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Cache hal config
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t core_nums; ///< CPU core numbers
|
||||
uint32_t l2_cache_size; ///< L2 cache size
|
||||
uint32_t l2_cache_line_size; ///< L2 cache line size
|
||||
} cache_hal_config_t;
|
||||
|
||||
/**
|
||||
* Cache init and cache hal context init
|
||||
*
|
||||
* @param config Cache hal config
|
||||
*/
|
||||
void cache_hal_init(const cache_hal_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Disable Cache
|
||||
*
|
||||
* Disable the ICache or DCache or both, of a certain level or all levels.
|
||||
* All the items in the corresponding Cache(s) will be invalideated.
|
||||
* Next request to these items will trigger a transaction to the physical memory
|
||||
*
|
||||
* @note If the autoload feature is enabled, this API will return until the ICache autoload is disabled.
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*/
|
||||
void cache_hal_disable(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Enable Cache
|
||||
*
|
||||
* Enable the ICache or DCache or both, of a certain level or all levels.
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*/
|
||||
void cache_hal_enable(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Suspend Cache
|
||||
*
|
||||
* Suspend the ICache or DCache or both, of a certain level or all levels.
|
||||
* This API suspends the CPU access to cache for a while, without invalidation.
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*/
|
||||
void cache_hal_suspend(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Resume Cache
|
||||
*
|
||||
* Resume the ICache or DCache or both, of a certain level or all levels.
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*/
|
||||
void cache_hal_resume(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Check if corresponding cache is enabled or not
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*
|
||||
* @return true: enabled; false: disabled
|
||||
*/
|
||||
bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Invalidate Cache supported addr
|
||||
*
|
||||
* Invalidate a Cache item for either ICache or DCache.
|
||||
*
|
||||
* @param vaddr Start address of the region to be invalidated
|
||||
* @param size Size of the region to be invalidated
|
||||
*
|
||||
* @return True for valid address. No operation if invalid
|
||||
*/
|
||||
bool cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size);
|
||||
|
||||
#if SOC_CACHE_WRITEBACK_SUPPORTED
|
||||
/**
|
||||
* @brief Writeback Cache supported addr
|
||||
*
|
||||
* Writeback the DCache item to external memory
|
||||
*
|
||||
* @param vaddr Start address of the region to writeback
|
||||
* @param size Size of the region to writeback
|
||||
*
|
||||
* @return True for valid address. No operation if invalid
|
||||
*/
|
||||
bool cache_hal_writeback_addr(uint32_t vaddr, uint32_t size);
|
||||
#endif //#if SOC_CACHE_WRITEBACK_SUPPORTED
|
||||
|
||||
#if SOC_CACHE_FREEZE_SUPPORTED
|
||||
/**
|
||||
* @brief Freeze Cache
|
||||
*
|
||||
* Freeze cache, CPU access to cache will be suspended, until the cache is unfrozen.
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*/
|
||||
void cache_hal_freeze(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Unfreeze cache
|
||||
*
|
||||
* Unfreeze cache, CPU access to cache will be restored
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*/
|
||||
void cache_hal_unfreeze(uint32_t cache_level, cache_type_t type);
|
||||
#endif //#if SOC_CACHE_FREEZE_SUPPORTED
|
||||
|
||||
/**
|
||||
* @brief Get cache line size, in bytes
|
||||
*
|
||||
* @param cache_level Level of the Cache(s)
|
||||
* @param type see `cache_type_t`
|
||||
*
|
||||
* @return cache line size, in bytes. 0 stands for no such cache in this type or level
|
||||
*/
|
||||
uint32_t cache_hal_get_cache_line_size(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Start cache preload for a region (manual preload)
|
||||
*
|
||||
* Preloads the given address range into cache, this can improve
|
||||
* performance when the region will be read soon.
|
||||
*
|
||||
* @param cache_level Level of the cache (e.g. CACHE_LL_LEVEL_EXT_MEM)
|
||||
* @param type CACHE_TYPE_DATA, CACHE_TYPE_INSTRUCTION, or CACHE_TYPE_ALL
|
||||
* @param vaddr Start virtual address of the region to preload
|
||||
* @param size Size in bytes. Should be cache-line aligned; if not,
|
||||
* the actual preloaded length is rounded down to cache-line boundary.
|
||||
* @param order preload order
|
||||
*/
|
||||
void cache_hal_preload(uint32_t cache_level, cache_type_t type, uint32_t vaddr, uint32_t size, cache_preload_order_t order);
|
||||
|
||||
/**
|
||||
* @brief Wait until cache preload started by cache_hal_preload() is done
|
||||
*
|
||||
* @param cache_level Level of the cache (must match the level used in cache_hal_preload)
|
||||
* @param type CACHE_TYPE_DATA, CACHE_TYPE_INSTRUCTION, or CACHE_TYPE_ALL
|
||||
*/
|
||||
void cache_hal_preload_wait_done(uint32_t cache_level, cache_type_t type);
|
||||
|
||||
/**
|
||||
* @brief Get Cache level and the ID of the vaddr
|
||||
*
|
||||
* @param vaddr_start virtual address start
|
||||
* @param len vaddr length
|
||||
* @param out_level cache level
|
||||
* @param out_id cache id
|
||||
*
|
||||
* @return true for valid, false for invalid addr or null pointer
|
||||
*/
|
||||
bool cache_hal_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/cache_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if SOC_CACHE_CNT_SUPPORTED
|
||||
/**
|
||||
* @brief Description of one cache profile counter unit
|
||||
*
|
||||
* A unit is one set of counters observing one traffic stream, e.g. the
|
||||
* instruction fetches of core 0 into the L1 cache.
|
||||
*/
|
||||
typedef struct {
|
||||
const char *name; /*!< Short human-readable name */
|
||||
uint8_t level; /*!< Cache level (1 or 2) */
|
||||
cache_profile_traffic_t traffic; /*!< Kind of traffic observed */
|
||||
int8_t core_id; /*!< Originating core, -1 if unknown/mixed */
|
||||
uint32_t counter_reg[CACHE_PROFILE_COUNTER_MAX]; /*!< Counter registers; 0 if the unit
|
||||
does not have that counter */
|
||||
} cache_profile_counter_unit_t;
|
||||
|
||||
extern const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Kind of traffic observed by a cache profile counter unit
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_PROFILE_TRAFFIC_INST, /*!< Instruction fetches */
|
||||
CACHE_PROFILE_TRAFFIC_DATA, /*!< Data accesses */
|
||||
CACHE_PROFILE_TRAFFIC_UNIFIED, /*!< Mixed/unknown (unified request bus) */
|
||||
} cache_profile_traffic_t;
|
||||
|
||||
/**
|
||||
* @brief One of the counters of a cache profile counter unit
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_PROFILE_COUNTER_HIT, /*!< Completed accesses ("hit" counter) */
|
||||
CACHE_PROFILE_COUNTER_MISS, /*!< Miss stall events ("miss" counter) */
|
||||
CACHE_PROFILE_COUNTER_CONFLICT, /*!< Requester conflicts */
|
||||
CACHE_PROFILE_COUNTER_NXTLVL_RD, /*!< Line fills from the next level */
|
||||
CACHE_PROFILE_COUNTER_NXTLVL_WR, /*!< Write-backs to the next level */
|
||||
CACHE_PROFILE_COUNTER_MAX,
|
||||
} cache_profile_counter_t;
|
||||
|
||||
typedef enum {
|
||||
CACHE_TYPE_DATA,
|
||||
CACHE_TYPE_INSTRUCTION,
|
||||
CACHE_TYPE_ALL //This means both ICache and DCache will be used. On some chips, I/D are controlled by a shared Cache. Also use this enum under this condition. See `SOC_SHARED_IDCACHE_SUPPORTED`.
|
||||
} cache_type_t;
|
||||
|
||||
/**
|
||||
* @brief Ibuses and Dbuses.
|
||||
*
|
||||
* @note
|
||||
* These enumurations are abstract concepts. Virtual address reside in one of these buses.
|
||||
* Therefore, use `cache_ll_l1_get_bus(bus_id, vaddr_start, len)` to convert your vaddr into buses first
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_BUS_IBUS0 = BIT(0),
|
||||
CACHE_BUS_IBUS1 = BIT(1),
|
||||
CACHE_BUS_IBUS2 = BIT(2),
|
||||
CACHE_BUS_DBUS0 = BIT(3),
|
||||
CACHE_BUS_DBUS1 = BIT(4),
|
||||
CACHE_BUS_DBUS2 = BIT(5),
|
||||
} cache_bus_mask_t;
|
||||
|
||||
/**
|
||||
* @brief Preload order
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_PRELOAD_ORDER_ASCENDING,
|
||||
CACHE_PRELOAD_ORDER_DESCENDING,
|
||||
} cache_preload_order_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,187 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <esp_types.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MMU hal config
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t core_nums; ///< CPU core numbers
|
||||
uint32_t mmu_page_size; ///< MMU page size
|
||||
} mmu_hal_config_t;
|
||||
|
||||
/**
|
||||
* MMU Hal layer initialisation
|
||||
*
|
||||
* @param config MMU hal config
|
||||
*/
|
||||
void mmu_hal_init(const mmu_hal_config_t *config);
|
||||
|
||||
/**
|
||||
* MMU Hal layer context initialisation
|
||||
*
|
||||
* @param config MMU hal config
|
||||
*/
|
||||
void mmu_hal_ctx_init(const mmu_hal_config_t *config);
|
||||
|
||||
/**
|
||||
* Unmap all the MMU table. After this all external memory vaddr are not available
|
||||
*/
|
||||
void mmu_hal_unmap_all(void);
|
||||
|
||||
/**
|
||||
* Helper functions to convert the MMU page numbers into bytes. e.g.:
|
||||
* - When MMU page size is 16KB, page_num = 2 will be converted into 32KB
|
||||
* - When MMU page size is 32KB, page_num = 2 will be converted into 64KB
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param page_num page numbers
|
||||
*
|
||||
* @return
|
||||
* length in byte
|
||||
*/
|
||||
uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num);
|
||||
|
||||
/**
|
||||
* Helper functions to convert bytes into MMU page numbers. e.g.:
|
||||
* - When MMU page size is 16KB, bytes = 64KB will be converted into 4 pages
|
||||
* - When MMU page size is 32KB, bytes = 64KB will be converted into 2 pages
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param bytes length in byte
|
||||
*
|
||||
* @return
|
||||
* length in CONFIG_MMU_PAGE_SIZE
|
||||
*/
|
||||
uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes);
|
||||
|
||||
/**
|
||||
* To map a virtual address block to a physical memory block
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param mem_type physical memory type, see `mmu_target_t`
|
||||
* @param vaddr start virtual address to be mapped
|
||||
* @param paddr start physical address to be mapped
|
||||
* @param len length to be mapped, in bytes
|
||||
* @param[out] out_len actual mapped length
|
||||
*
|
||||
* @note vaddr and paddr should be aligned with the mmu page size, see CONFIG_MMU_PAGE_SIZE
|
||||
*/
|
||||
void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len);
|
||||
|
||||
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE
|
||||
/**
|
||||
* Map a PSRAM physical range to virtual memory without setting the encryption
|
||||
* SENSITIVE bit on each MMU entry. Used only for the explicitly carved-out
|
||||
* unencrypted PSRAM region (see CONFIG_SPIRAM_ENC_EXEMPT).
|
||||
*
|
||||
* @param vaddr start virtual address (MMU-page-aligned)
|
||||
* @param paddr start physical address (MMU-page-aligned)
|
||||
* @param len length in bytes
|
||||
*/
|
||||
void mmu_hal_map_region_no_enc(uint32_t vaddr, uint32_t paddr, uint32_t len);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* To unmap a virtual address block that is mapped to a physical memory block previously
|
||||
*
|
||||
* @param[in] mmu_id MMU ID
|
||||
* @param[in] vaddr start virtual address
|
||||
* @param[in] len length to be unmapped, in bytes
|
||||
*/
|
||||
void mmu_hal_unmap_region(uint32_t mmu_id, uint32_t vaddr, uint32_t len);
|
||||
|
||||
/**
|
||||
* Convert virtual address to physical address
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr virtual address
|
||||
* @param[out] out_paddr physical address
|
||||
* @param[out] out_target Indicating the vaddr/paddr is mapped on which target, see `mmu_target_t`
|
||||
*
|
||||
* @return
|
||||
* - true: virtual address is valid
|
||||
* - false: virtual address isn't valid
|
||||
*/
|
||||
bool mmu_hal_vaddr_to_paddr(uint32_t mmu_id, uint32_t vaddr, uint32_t *out_paddr, mmu_target_t *out_target);
|
||||
|
||||
/**
|
||||
* Convert physical address to virtual address
|
||||
*
|
||||
* @note This function can only find the first match virtual address.
|
||||
* However it is possible that a physical address is mapped to multiple virtual addresses.
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr physical address
|
||||
* @param target physical memory target, see `mmu_target_t`
|
||||
* @param type virtual address type, could be instruction or data
|
||||
* @param[out] out_vaddr virtual address
|
||||
*
|
||||
* @return
|
||||
* - true: found a matched vaddr
|
||||
* - false: not found a matched vaddr
|
||||
*/
|
||||
bool mmu_hal_paddr_to_vaddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target, mmu_vaddr_t type, uint32_t *out_vaddr);
|
||||
|
||||
/**
|
||||
* Check if the vaddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param vaddr_start start of the virtual address
|
||||
* @param len length, in bytes
|
||||
* @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t`
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
bool mmu_hal_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type);
|
||||
|
||||
/**
|
||||
* Check if the paddr region is valid
|
||||
*
|
||||
* @param mmu_id MMU ID
|
||||
* @param paddr_start start of the physical address
|
||||
* @param len length, in bytes
|
||||
*
|
||||
* @return
|
||||
* True for valid
|
||||
*/
|
||||
bool mmu_hal_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len);
|
||||
|
||||
#if SOC_MMU_PER_EXT_MEM_TARGET
|
||||
/**
|
||||
* Get MMU ID from MMU target
|
||||
*
|
||||
* @param target MMU target
|
||||
*
|
||||
* @return
|
||||
* MMU ID
|
||||
*/
|
||||
uint32_t mmu_hal_get_id_from_target(mmu_target_t target);
|
||||
|
||||
/**
|
||||
* Get MMU ID from vaddr
|
||||
*
|
||||
* @param vaddr Virtual address
|
||||
*
|
||||
* @return
|
||||
* MMU ID
|
||||
*/
|
||||
uint32_t mmu_hal_get_id_from_vaddr(uint32_t vaddr);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
MMU_MEM_CAP_EXEC = BIT(0),
|
||||
MMU_MEM_CAP_READ = BIT(1),
|
||||
MMU_MEM_CAP_WRITE = BIT(2),
|
||||
MMU_MEM_CAP_32BIT = BIT(3),
|
||||
MMU_MEM_CAP_8BIT = BIT(4),
|
||||
} mmu_mem_caps_t;
|
||||
|
||||
/**
|
||||
* MMU Page size
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_PAGE_8KB = 0x2000,
|
||||
MMU_PAGE_SIZE_MIN = MMU_PAGE_8KB,
|
||||
MMU_PAGE_16KB = 0x4000,
|
||||
MMU_PAGE_32KB = 0x8000,
|
||||
MMU_PAGE_64KB = 0x10000,
|
||||
MMU_PAGE_128KB = 0x20000,
|
||||
MMU_PAGE_256KB = 0x40000,
|
||||
MMU_PAGE_SIZE_MAX = MMU_PAGE_256KB,
|
||||
} mmu_page_size_t;
|
||||
|
||||
/**
|
||||
* MMU virtual address flags type
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_VADDR_DATA = BIT(0),
|
||||
MMU_VADDR_INSTRUCTION = BIT(1),
|
||||
} mmu_vaddr_t;
|
||||
|
||||
/**
|
||||
* External physical memory
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_TARGET_FLASH0 = BIT(0),
|
||||
MMU_TARGET_PSRAM0 = BIT(1),
|
||||
} mmu_target_t;
|
||||
|
||||
/**
|
||||
* MMU table id
|
||||
*/
|
||||
typedef enum {
|
||||
MMU_TABLE_CORE0,
|
||||
MMU_TABLE_CORE1,
|
||||
} mmu_table_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,9 @@
|
||||
[mapping:esp_hal_cache]
|
||||
archive: libesp_hal_cache.a
|
||||
entries:
|
||||
if APP_BUILD_TYPE_PURE_RAM_APP = n:
|
||||
if IDF_TARGET_ESP32 = y:
|
||||
cache_hal_esp32 (noflash)
|
||||
else:
|
||||
cache_hal (noflash)
|
||||
mmu_hal (noflash)
|
||||
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <sys/param.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_err.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/mmu_hal.h"
|
||||
#include "hal/mmu_ll.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "rom/cache.h"
|
||||
#include "esp_rom_caps.h"
|
||||
|
||||
typedef struct {
|
||||
uint8_t core_nums;
|
||||
} mmu_hal_context_t;
|
||||
|
||||
static mmu_hal_context_t s_ctx;
|
||||
|
||||
void mmu_hal_ctx_init(const mmu_hal_config_t *config)
|
||||
{
|
||||
s_ctx.core_nums = config->core_nums;
|
||||
}
|
||||
|
||||
void mmu_hal_init(const mmu_hal_config_t *config)
|
||||
{
|
||||
mmu_hal_ctx_init(config);
|
||||
|
||||
#if ESP_ROM_RAM_APP_NEEDS_MMU_INIT
|
||||
ROM_Boot_Cache_Init();
|
||||
#endif
|
||||
mmu_ll_set_page_size(0, config->mmu_page_size);
|
||||
mmu_hal_unmap_all();
|
||||
}
|
||||
|
||||
void mmu_hal_unmap_all(void)
|
||||
{
|
||||
#if SOC_MMU_PER_EXT_MEM_TARGET
|
||||
mmu_ll_unmap_all(MMU_LL_FLASH_MMU_ID);
|
||||
mmu_ll_unmap_all(MMU_LL_PSRAM_MMU_ID);
|
||||
#else
|
||||
for (int i = 0; i < s_ctx.core_nums; i++) {
|
||||
mmu_ll_unmap_all(i);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return page_num << shift_code;
|
||||
}
|
||||
|
||||
uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes)
|
||||
{
|
||||
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
|
||||
uint32_t shift_code = 0;
|
||||
switch (page_size) {
|
||||
case MMU_PAGE_64KB:
|
||||
shift_code = 16;
|
||||
break;
|
||||
case MMU_PAGE_32KB:
|
||||
shift_code = 15;
|
||||
break;
|
||||
case MMU_PAGE_16KB:
|
||||
shift_code = 14;
|
||||
break;
|
||||
default:
|
||||
HAL_ASSERT(shift_code);
|
||||
}
|
||||
return bytes >> shift_code;
|
||||
}
|
||||
|
||||
void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len)
|
||||
{
|
||||
uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
|
||||
HAL_ASSERT(vaddr % page_size_in_bytes == 0);
|
||||
HAL_ASSERT(paddr % page_size_in_bytes == 0);
|
||||
HAL_ASSERT(mmu_ll_check_valid_paddr_region(mmu_id, paddr, len));
|
||||
HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INSTRUCTION));
|
||||
|
||||
uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes;
|
||||
uint32_t entry_id = 0;
|
||||
uint32_t mmu_val; //This is the physical address in the format that MMU supported
|
||||
|
||||
*out_len = mmu_hal_pages_to_bytes(mmu_id, page_num);
|
||||
mmu_val = mmu_ll_format_paddr(mmu_id, paddr, mem_type);
|
||||
|
||||
while (page_num) {
|
||||
entry_id = mmu_ll_get_entry_id(mmu_id, vaddr);
|
||||
mmu_ll_write_entry(mmu_id, entry_id, mmu_val, mem_type);
|
||||
vaddr += page_size_in_bytes;
|
||||
mmu_val++;
|
||||
page_num--;
|
||||
}
|
||||
}
|
||||
|
||||
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE
|
||||
void mmu_hal_map_region_no_enc(uint32_t vaddr, uint32_t paddr, uint32_t len)
|
||||
{
|
||||
uint32_t mmu_id = MMU_LL_PSRAM_MMU_ID;
|
||||
uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
|
||||
HAL_ASSERT(vaddr % page_size_in_bytes == 0);
|
||||
HAL_ASSERT(paddr % page_size_in_bytes == 0);
|
||||
HAL_ASSERT(mmu_ll_check_valid_paddr_region(mmu_id, paddr, len));
|
||||
// Restrict to data vaddr space — unencrypted PSRAM must never back code/rodata.
|
||||
HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA));
|
||||
|
||||
uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes;
|
||||
uint32_t mmu_val = mmu_ll_format_paddr(mmu_id, paddr, MMU_TARGET_PSRAM0);
|
||||
|
||||
while (page_num) {
|
||||
uint32_t entry_id = mmu_ll_get_entry_id(mmu_id, vaddr);
|
||||
mmu_ll_write_entry_no_enc(mmu_id, entry_id, mmu_val);
|
||||
vaddr += page_size_in_bytes;
|
||||
mmu_val++;
|
||||
page_num--;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void mmu_hal_unmap_region(uint32_t mmu_id, uint32_t vaddr, uint32_t len)
|
||||
{
|
||||
uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
|
||||
HAL_ASSERT(vaddr % page_size_in_bytes == 0);
|
||||
HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INSTRUCTION));
|
||||
|
||||
uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes;
|
||||
uint32_t entry_id = 0;
|
||||
while (page_num) {
|
||||
entry_id = mmu_ll_get_entry_id(mmu_id, vaddr);
|
||||
mmu_ll_set_entry_invalid(mmu_id, entry_id);
|
||||
vaddr += page_size_in_bytes;
|
||||
page_num--;
|
||||
}
|
||||
}
|
||||
|
||||
bool mmu_hal_vaddr_to_paddr(uint32_t mmu_id, uint32_t vaddr, uint32_t *out_paddr, mmu_target_t *out_target)
|
||||
{
|
||||
HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, 1, MMU_VADDR_DATA | MMU_VADDR_INSTRUCTION));
|
||||
uint32_t entry_id = mmu_ll_get_entry_id(mmu_id, vaddr);
|
||||
if (!mmu_ll_check_entry_valid(mmu_id, entry_id)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
|
||||
uint32_t offset = (uint32_t)vaddr % page_size_in_bytes;
|
||||
|
||||
*out_target = mmu_ll_get_entry_target(mmu_id, entry_id);
|
||||
uint32_t paddr_base = mmu_ll_entry_id_to_paddr_base(mmu_id, entry_id);
|
||||
*out_paddr = paddr_base | offset;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool mmu_hal_paddr_to_vaddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target, mmu_vaddr_t type, uint32_t *out_vaddr)
|
||||
{
|
||||
HAL_ASSERT(mmu_ll_check_valid_paddr_region(mmu_id, paddr, 1));
|
||||
|
||||
uint32_t mmu_val = mmu_ll_format_paddr(mmu_id, paddr, target);
|
||||
int entry_id = mmu_ll_find_entry_id_based_on_map_value(mmu_id, mmu_val, target);
|
||||
if (entry_id == -1) {
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
|
||||
uint32_t offset = paddr % page_size_in_bytes;
|
||||
uint32_t vaddr_base = mmu_ll_entry_id_to_vaddr_base(mmu_id, entry_id, type);
|
||||
if (vaddr_base == 0) {
|
||||
return false;
|
||||
}
|
||||
*out_vaddr = vaddr_base | offset;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool mmu_hal_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
|
||||
{
|
||||
return mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr_start, len, type);
|
||||
}
|
||||
|
||||
bool mmu_hal_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
|
||||
{
|
||||
return mmu_ll_check_valid_paddr_region(mmu_id, paddr_start, len);
|
||||
}
|
||||
|
||||
#if SOC_MMU_PER_EXT_MEM_TARGET
|
||||
uint32_t mmu_hal_get_id_from_target(mmu_target_t target)
|
||||
{
|
||||
return (target == MMU_TARGET_FLASH0) ? MMU_LL_FLASH_MMU_ID : MMU_LL_PSRAM_MMU_ID;
|
||||
}
|
||||
|
||||
uint32_t mmu_hal_get_id_from_vaddr(uint32_t vaddr)
|
||||
{
|
||||
return mmu_ll_vaddr_to_id(vaddr);
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user