Merge branch 'feature/esp32h4_flash_support' into 'master'

feat(spi_flash): Add exclusive support for ESP32H4

Closes IDF-12290, IDF-12389, and IDF-15616

See merge request espressif/esp-idf!47679

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -215,6 +215,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED
+    bool
+    default y
+
 config SOC_ECDSA_SUPPORTED
     bool
     default y
@@ -871,6 +875,10 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
     bool
     default y
 
+config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
+    bool
+    default y
+
 config SOC_MEMSPI_IS_INDEPENDENT
     bool
     default y

components/soc/esp32h4/include/soc/clk_tree_defs.h

@@ -274,7 +274,7 @@ typedef enum {
  * @brief Type of SPI clock source.
  */
 typedef enum {
-    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,     /*!< Select XTAL as SPI source clock */
+    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,     /*!< Select PLL_F48M as SPI source clock */
     SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,            /*!< Select XTAL as SPI source clock */
     SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,    /*!< Select PLL_48M as SPI source clock */
     SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,      /*!< Select RC_FAST as SPI source clock */

components/soc/esp32h4/include/soc/soc_caps.h

@@ -89,6 +89,7 @@
 #define SOC_WDT_SUPPORTED               1
 #define SOC_RTC_WDT_SUPPORTED           1
 #define SOC_SPI_FLASH_SUPPORTED         1
+#define SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED    1
 #define SOC_ECDSA_SUPPORTED             1
 #define SOC_SPIRAM_SUPPORTED            1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
@@ -376,6 +377,7 @@
 #define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
 #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
 #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR        (1)
+#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP          (1)
 #define SOC_MEMSPI_IS_INDEPENDENT                          1
 
 #define SOC_MEMSPI_ENCRYPTION_ALIGNMENT           16    /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */

components/soc/esp32h4/register/soc/spi1_mem_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -417,6 +417,30 @@ extern "C" {
 #define SPI_MEM_STATUS_M  (SPI_MEM_STATUS_V << SPI_MEM_STATUS_S)
 #define SPI_MEM_STATUS_V  0x0000FFFFU
 #define SPI_MEM_STATUS_S  0
+/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0;
+ *  Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define SPI_MEM_WB_MODE    0x000000FFU
+#define SPI_MEM_WB_MODE_M  (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S)
+#define SPI_MEM_WB_MODE_V  0x000000FFU
+#define SPI_MEM_WB_MODE_S  16
+/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0;
+ *  Mode bits length for flash fast read mode.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define SPI_MEM_WB_MODE_BITLEN    0x00000007U
+#define SPI_MEM_WB_MODE_BITLEN_M  (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S)
+#define SPI_MEM_WB_MODE_BITLEN_V  0x00000007U
+#define SPI_MEM_WB_MODE_BITLEN_S  24
+/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0;
+ *  Mode bits is valid while this bit is enable. 1: enable 0: disable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define SPI_MEM_WB_MODE_EN    (BIT(27))
+#define SPI_MEM_WB_MODE_EN_M  (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S)
+#define SPI_MEM_WB_MODE_EN_V  0x00000001U
+#define SPI_MEM_WB_MODE_EN_S  27
 
 /** SPI_MEM_MISC_REG register
  *  SPI1 misc register